New: 8MB ALT RAM board

[alanh]

Hi folks,

Ideal for those folk who have TOS 2.06 already in their MegaST's or have my IDE board with TOS 2.06 already done.

If you have my IDE board in the MegaST, then just replace the bus adapter with this, and run a small program in the AUTO folder, and hey presto. An additional 8MB Alternate RAM.

photo.JPG

Anyone want one ? Price is only 55GBP plus shipping. PM me if interested as I only have 8 available.

If you send back the old bus adapter I'll credit you back 5GBP when received.

[joska]

Interesting What about combining alt-RAM and IDE on a single PCB? I would be interested in one for my old STM.

[alanh]

Yes, it's an option. But the price would be quite high because of the combined board, and I'm not sure the numbers add up to produce for the STFM as I haven't sold that many IDE boards for the MegaST/STFM anyway.

[exxos]

Yes, it's an option. But the price would be quite high because of the combined board, and I'm not sure the numbers add up to produce for the STFM as I haven't sold that many IDE boards for the MegaST/STFM anyway.

I hit similar problem with Alt-ram for STFM, even though I was mid-way though producing the MagnumST, there isn't any demand to complete the project. Though there is a small chance that Alt-ram might be added on one of CPU booster boards that are being worked on. Though again, similar problems of how many people would buy the booster, and pay more for the Alt-ram ontop of it. Its possible IDE could be added also, but it is increasing the cost up each time, and space inside the ST is a huge problem also.

Looking at the size of the RAM chip you have on there, its not too large, but I wonder if there is a small flash chip which is similar in size that could be used as a hard dive instead of adding a actual card ? Cost of a flash chip probably be a lot more, but again, its a space problem.

[frank.lukas]

It is possible to remove the Mega ST Bus Connector and works the Board in a Atari 1040ST/STE (STE with PLCC-DIL Adapter) ?

[alanh]

Yes, but I'm considering making a new IDE board with ALTRAM on for the STE as it seems there are more people wanting IDE on those platforms than STFM.

[alexh]

I would be interested. But what use is alt RAM on the ST? And what does it do to compatibility?

[Guest]

in the boot process loading of drivers can happen

to enable more st ram etc

so there should be some sort of mmu address decoding power on by pass used
and first encoding by the driver once its loaded to interpolate the needed hardware addresses

the only issues with st level and ste etc level is the need for more MAD address lines

and the only way to do that is to strobe the MAD in a different way

this way we can have up to 1GB of ram ... st tt etc

the mmu is the issue and the way it strobes can be over and interlaced to allow a simple 74 ttl decoder to be used
to provide extra addresses when its enabled with DTACK transaction and a counter... linked to MAD output
to allow for original mode and over/interlaced mode

what needs to be done is MAD bus split to nibbles and a control nibble usually its 10 MAD lines 0-9 or 11 0-10 the falcon uses 0-10

so 8 bits + 2 control bits {nibble mode}

[alanh]

I would be interested. But what use is alt RAM on the ST? And what does it do to compatibility?

Hi Alex, interested in what specifically as the thread is bouncing around configurations ?

As for compatibility, without the AUTO folder program, TOS doesn't see the memory.

[alanh]

in the boot process loading of drivers can happen

to enable more ram

so there should be some sort of mmu address decoding
and first encoding by the driver once its loaded

the only issues with st level and ste etc level is the need for more MAD address lines

and the only way to do that is to strobe the MAD in a different way

this way we can have up to 1GB of ram ... st tt etc

the mmu is the issue and the way it strobes can be over and interlaced to allow a simple 74 ttl decoder to be used
to provide extra addresses when its enabled with DTACK transaction and a counter... linked to MAD output
to allow for original mode and over/interlaced mode

what needs to be done is MAD bus split to nibbles and a control nibble usually its 10 MAD lines 0-9 or 11 0-10 the falcon uses 0-10

so 8 bits + 2 control bits {nibble mode}

Hi Simbo,

Unfortunately the ST (i.e. the 68000 CPU) can't address more than 16MB of memory, no where near 1GB.

Also, it has nothing to do with the MMU's MAD lines.

ALTRAM is not even seen by the MMU. It's CPU access only.

[Guest]

this is rubbish

the 68000 can address 128GB of physical space

slowly yes but it will allow up to 128GB hdd a hdd is physical ram

so no alan your wrong on this occasion

any device attached to an atari is treated as RAM

its all down to a memory table

so you can have fast faster or hdd

all devices are area so if the mpu can address a hdd it can also address a ssd

perhaps someone needs to interface a ssd to there atari at a ram level

granted its not fast access but its massive

[alanh]

Simbo... please....

[Guest]

you know im right

however a nice project and im not trashing the thread

so.... 128GB i think hd driver allows 138GB as a single partition and this is physical space same as ram
just controlled in a different way as interlaced space

68030 has its own mmu it can address !!! 128GB of ram !!!

perhaps people need to work around limits with a flashable controller instead of a dead stop glue or mmu

plcc riser board added socket and a clpd is the way modern french cpld spring to mind

[alanh]

Your not, and I'll refrain from replying more to this. Stick to the ST here. i.e. 68000.

[Guest]

it does not matter if the mpu has its own controller or not
even a 6800 can address 128GB of space

people with st mega st etc just cant see past the limits

you interpolate the mmu /glue MAD output the driver switches this mode on the machine then can address more physical space

the first thing it says in the 68000 books ive read is that the 68000 can address 128GB of space

how its arranged is up to the fabrication and design

the 68000 was the first to allow double address mode

address ram twice so this is 16 bit X 16 bits

65536 states mux 65536 address... this is 128GB

this mode isnt used in ANY atari except the TT and its only partial

[joska]

Yes, but I'm considering making a new IDE board with ALTRAM on for the STE as it seems there are more people wanting IDE on those platforms than STFM.

I would be interested in one, depending on price.

[alanh]

Right, I wouldn't make them without getting pre-orders as they'd be more expensive. Would you pay between 80 to 100 GBP ?

[joska]

Sorry, that's a bit much. I think I paid around 40 GBP for kipper's 8Mb/IDE-adapter for my Amiga 500. Currently the 8 extra Mb is not worth 80-100 for me, sorry.

[alanh]

Exactly. The STe adapter for the PLCC I'm thinking of using puts the price at 30GBP before I start work. Then I'm currently using an SRAM 8Mb chip which also isn't cheap.

I think Kippers Amiga version is just a 68000 socket which sets the bar much lower for upgrades.

So I'll probably only do one or two for my use.

[alanh]

joska, if I didn't use this adapter part and fallback to the pin headers in the current IDE design, it probably comes down to 50GBP to 70GBP. Is that range more palateable ? Or is even 70 too high ?

[delvis]

Alan,

Looks like a great project. I will more than likely buy one. It may be a little while though. When I bought the IDE board I bought two base mounts. So if I turn them both in I get 10 off? Might just cover my shipping costs.

Delvis

[joska]

joska, if I didn't use this adapter part and fallback to the pin headers in the current IDE design, it probably comes down to 50GBP to 70GBP. Is that range more palateable ? Or is even 70 too high ?

I think that 50-70 is a reasonable price.

[AtariZoll]

in the boot process loading of drivers can happen
to enable more st ram etc
so there should be some sort of mmu address decoding power on by pass used
and first encoding by the driver once its loaded to interpolate the needed hardware addresses
the only issues with st level and ste etc level is the need for more MAD address lines
and the only way to do that is to strobe the MAD in a different way
this way we can have up to 1GB of ram ... st tt etc
the mmu is the issue and the way it strobes can be over and interlaced to allow a simple 74 ttl decoder to be used
to provide extra addresses when its enabled with DTACK transaction and a counter... linked to MAD output
to allow for original mode and over/interlaced mode
what needs to be done is MAD bus split to nibbles and a control nibble usually its 10 MAD lines 0-9 or 11 0-10 the falcon uses 0-10
so 8 bits + 2 control bits {nibble mode}

Well, let's say that you are right in this - even if most of people here don't think so, I'm sure. So, what about that instead writings here you start to design such RAM controller for ST and share with us, or start to sale ? I have here some 128MB SDRAM modules, and would like to see them in my Atari. So, please do that 1GB or whatever RAM capable expansion for good old MC68000 .

[Guest]

prob is your 68000 runs too slow having to control {supervise} a mmu / glue etc
so you need a 68030 or 40 in atari st land
to gain a dedicated mmu
on chip
then your machine can do a dance,,,, and control up to 138GB of ram
you need a decent 68030 setup
even the falcon got bless its sole cant do the dance
and the 68030 has never really been used past 2nd stop
nor has its own mcu
perhaps people with st need to replace the 68000 and buss with a riser
the rest is up too you
a 68000 can physically address 138GB of space a 68030 or later can do the same with less space chips etc as its mmu is on board the mpu
and is a good thing for people to make
st 68030... at least.. add in
this way you can have no limits
non that i can see
and the mechanism is there for all this


where is the 68030 addin plug in to the 68000 + some lines added vga etc from the 68030 {lots of cheep ic same chips as the TT i got 20 for less than 50 quid}

you can slag reality all day but the only way to overcome st or ste or mega ste limits is to employ a 68030 and mount both st and tt ram in the riser board
at the same time a single fpga ic for vga,,, output too replace the shifter... the shifter like the falcon uses becomes just a function set

[AtariZoll]

Hmmm... should I quote more Simbo ? You said that "the first thing it says in the 68000 books ive read is that the 68000 can address 128GB of space" I did not see it.
So, answer this: how you can solve addressing of more than 16MB with CPU which have only 23 address lines + UDS, LDS lines ?
You mentioned something about expanding MMU etc. And don't come with low speed of 68000. Let's talk about 68000 at 32 MHz for instance.
And of course, don't come with some RAM bank switchings - it is known over 30 years.

SW side of this: CPU registers are 32-bit, what means max 4GB addressable. So, how you will give command to read something from address beyond that ?

"address ram twice so this is 16 bit X 16 bits
65536 states mux 65536 address... this is 128GB"
128 is 32x4 . How you came to this ridiculous value of 128GB - really makes no sense . Ah, there was such limit by PC BIOS-es for IDE drives in past ...

Please give concrete and short answers on concrete questions, and don't start some long "dance to 138GB"
I don't want to replace CPU to 68030. It will make SW compatibility problems.