Main HW / Emulator constants (MFP/CPU/DMA sound)

[ljbk]

Steem will not be left behind!

Since in Steem there's no independent DMA clock, it is computed using CPU clock, it is important to have the latter right.

Sometimes the value for MFP_VBL is different, eg 8021286, the others are more stable. Could be a problem with VBI, that isn't always perfect in Steem.

Hi !

Thanks for updating STeem.
Those values are quite allright.
The values may differ as there is a 24 cycles loop. So the loop stop can differ by 24 cycles or one 60 KHz interrupt counted or not.That is why with my real STF i get either 160244 cycles or from time to time 160268 VBL cycles.

You can check here:
http://www.atari-forum.com/viewtopic.ph ... 20#p229120
to get the last version 002 that now works with NTSC/60Hz and Mono/71 Hz.

Paulo.

[ljbk]

Hi Nicolas !

I have one last ( ) question about the STE sound DMA.

Assuming that the FIFO is only filled when the Shifter is not reading data from memory, this means that in Colour modes the FIFO will not be updated during 320 cycles while the 320 pixels data in Low resolution or 640 pixels data in Medium resolution are read, right ?
This also means that in overscan modes, the reads will happen later, after the right border bitmap has been displayed, and so in case of a 230 bytes line, only 52 cycles are left to read up to 8 bytes of sound data in stereo, right ?
This should mean that in Mono mode, the FIFO will be updated more frequently, as the Display Enable will be active for 200 cycles and inactive for 24 cycles where up to 4 bytes have to be read to the FIFO, right ?
We should also have more regular reads during the top and bottom borders as the display is not enabled, right?
FInally, this should mean that when you start the DMA to play, the sound might only really be played after up to 460 cyles in overscan mode, right ?
Does Hatari support all this ?

Thanks,
Paulo.

[npomarede]

Ooops, I didn't see your post at the time.
So yes, I think the FIFO is only filled when display is disabled, which in the "worst" case would be after cycle 460 when removing left/right border in low/med res.
From my computation, even when removing left/right border, you still have enough cycles to keep the FIFO filled at 50066 Hz stereo.

But it would be an interesting thing to test on a real STE : play a 50066 Hz stereo sound during an overscan screen and hear if sound is altered or not (maybe there's already a demo doing this, I haven't checked)

From the point of Hatari, I don't handle this with such fine-grained method as waiting for the exact cycle when display is disabled to refill the DMA FIFO ; I just refilled it on every HBL, without checking for how many cycles are still free on the display line (as I assume there will always be enough cycles to keep the FIFO filled).
When reading the DMA sound current address (and being synchronised with ff8209), this can be used to check if the machine is a real STE or Hatari, because there can be 2 bytes difference sometimes in the way this counter is updated (and when).

Nicolas

[ljbk]

Thanks for your reply.

Paulo.

[Cyprian]

Here some my tests.

Mega STE first pass:

• VBL CYCLES: 160244 (160256 / 8 MHz)
  MFP_VBL CLOCK: 8021025 (IF CPU @ 8 MHz)
  MFPCALC CLOCK: 8020413
  TIME_LP CLOCK: 8020541
  SOUND DMA: 50067

Mega STE second pass:

• VBL CYCLES: 160244 (160256 / 8 MHz)
  MFP_VBL CLOCK: 8021025 (IF CPU @ 8 MHz)
  MFPCALC CLOCK: 8020413
  TIME_LP CLOCK: 8020566
  SOUND DMA: 50068

1040STE:

• VBL CYCLES: 160244 (160256 / 8 MHz)
  MFP_VBL CLOCK: 8020894 (IF CPU @ 8 MHz)
  MFPCALC CLOCK: 8020282
  TIME_LP CLOCK: 8020467
  SOUND DMA: 50067

[ljbk]

Hi !

Thanks for your input.
Latest data and test tool is available here:
http://www.atari-forum.com/viewtopic.php?f=15&t=24862

Paulo.

[Cyprian]

ok, I do that new test on my STE, MSTE and TT.

what about Mega STE 8/16MHz and cache setup? does it matter?

[ljbk]

ok, I do that new test on my STE, MSTE and TT.

what about Mega STE 8/16MHz and cache setup? does it matter?

8/16/32/xx MHz are not a problem.

Cache will cause an inflated CPU rate for the pure cycle count test.
For the timer / relative speed, cache will not change anything.
You can check the DarkLord "special" machines results at the HW topic.

Just test and check the results by yourself


Paulo.