The timeline is completely unknown, sadly! I'm fitting in doing this board in-between work and having two young kids, so I really don't get a lot of time to work on it. Although now I have *something* working, it should speed up a bit. I've spent many weeks arsing about in the evenings just trying to get RGB signals level converted into the FPGA and stable, all of which is just down to the fact I'm learning everything as I go along. I've got no background in electronics, and there's a whole lot about electrics I had no concept of until I started this. However I'm a techy coder type by trade, so once I've got a load of signals coming into the FPGA all nice, then the VHDL coding part is something that I'm a lot happier with...
I'm not sure about cost yet. I'm using a little £14 FPGA board from China and will need a couple of level converters (one for video and one for STE digital audio), an ADC for the YM audio, an HDMI repeater to turn the LVDS lines into something a little more universally friendly for HDMI TV's and monitors and an HDMI connector. So probably not more than about £10-15 worth of bits. But then there's getting PCB's made (which actually looks reasonably cheap from China) and populating them.
As I said I'm learning all this as I go along, so we'll find out.
Once things are running on a more complete prototype, I'll see if anyone with more experience in this stuff is interested in helping make a batch of final boards.
The fundamentals of this project for video out are relatively simple, really. HDMI is just sending digital RGB and clock data to a monitor -- so if you can get digital RGB and a clock signal from the motherboard, it doesn't take much effort to squirt this data over HDMI. One issue is that you have to use a standard 50Hz mode to get the monitor to recognise it -- in this case 576p (720x576). All sync data is generated by the FPGA and the ST video data is inlayed into the sync signals.
Getting audio working will be a good challenge in itself. The audio packets are transmitted during blanking periods in the video data. I've not looked into this in any detail yet, but it looks like it'll be fun as I'll be writing the audio part from scratch based on some VHDL source I found on the web for the video out.