obo wrote:
From the notes I made last year, I have the bit pattern of "000101001" written down, which is an extra leading zero bit ahead of the 0x29 pattern you mention. I'll have to check it, but I have a feeling it didn't work if the leading bit was a 1 - I'll try out 01 29 when I get a chance. It's also worth noting that this killerbit pattern works anywhere in the bit-stream - it doesn't have to be aligned on a byte boundary to be triggered.
Does the book have any more details on what causes it? Is it just the address mark decoder being enabled?
yes indeed it has. The book is VERY detailed
in MFM code:
00-F4 is written as is
F5 is written as sync byte A1 without any clock info, AND the checksum register is initialized to CDB4
F6 is written as sync byte C2, no CRC modif, and C2 is not detected by READ ADR or READ SECT
F7 writes the checksum, next byte is written as is
F8-FF adress marks
btw, short MFM explanation:
0 bit: write as x0
1 bit: write as 01
(x means complement of previous bit) this introduces inside the bytes some regular clock
so writing gives
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1 0 1 0 0 0 0 1 = the written byte (an $A1)
0100010010101001 = the MFM coding
NOTE: somehow the BBS is not formatting code as fixed width, at least not in preview, or not in Mozilla.
ok, now what does "writing A1 without clock" mean
well it has no clock between bit 4 and 5 (with $C2 it's bit 3 and 4)
so it looks like this
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0100010010101001 = normal A1
0100010010001001 = sync A1
the controller has an 'adress mark detector' triggering on missing clock and signals the FDC when it sees the bit pattern
during READ TRACK the adress mark detector is NOT switched off
after the index pluse the controller reads the bits (or the clocks) until a syncbyte
the first sync byte gets read as C2 or 14 and sometimes as 0A
Unfortunately the resync is done on the 000101001 pattern of 9 bits, this happens with
$29 and previous lower bit at 0
$52, $53 and 2 previous bits 0
$A4,$A5,$A6,$A7 and 3 previous bits 0
$14 and following byte's high bit set (bit 7)
$0A, $8A and following byte having bit6 set and bit 7 zero (e.g. $43)
$05, $45, $85, $C5 and following byte with bit 6 & 7 zero and bit 5 set (e.g. $21)
now that sync creates a half bit shift in the following data, and the controller now reads
clock bits as data bits.
This is great on track 41 ($29)
the adress mark looks like this
A1 A1 A1 FE 29 00 01 02 ....
and read track reads
14 A1 A1 FE 14 7F FE 7C ...
but why does it read $29 with preceding 0 bit as sync?
well it's a BUG !
in MFM it looks like this
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1010010001001001
0 0 1 0 1 0 0 1 = $29
1 1 0 0 0 0 1 0 = $C2
so the controller confuses data and clock bytes, sees a $C2 and syncs on that
result, it shifts everything by a half bit
Georges