Minimig RTG possible?

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BBond007
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Re: Minimig RTG possible?

Post by BBond007 »

JimDrew wrote:Picasso96 supports screen dragging. The Cybergraphics developer APIs were available for any company making products that needed low-level access. I got the APIs so I could write video drivers for FUSION and PCx, after signing a NDA of course.
Are you sure about that?

I had several Amiga graphics cards, but all used CGFX. For CGFX it worked but did not actually switch video modes like native Amiga chipset.

But I have used Amiberry on RetroPie (and UAE) with Picasso96 emulation and there is no screen dragging as far screens I can see...

Picasso96 FAQ:
http://cd.textfiles.com/amigama/amigama ... 6/FAQ.html


Q: Why is there no screen dragging with Picasso96?
A: Hmmm, the sad thing is: VGA chips do not have the features the Amiga Copper offers. There are too many restrictions:
you can do split screen, but you can only show two screens at the same time,
the screen width and RGB formats have to be the same, or it will look very strange,
if both screens are chunky they should use the same palette or it will...
the base address of the second screen must be 0 (ZERO), i.e. when this is not the case, then you will have to move the screen to that position. But this interferes with the memory management of Picasso96...
Last edited by BBond007 on Thu Jan 31, 2019 4:05 am, edited 1 time in total.
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Re: Minimig RTG possible?

Post by JimDrew »

Works fine on my real A3000 w/Picasso IV board. You do need the screen resolutions to be the same, so standard (promoted) Amiga screens all work together without any issues.
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Re: Minimig RTG possible?

Post by fpgaarcade »

Hi all.
We've released our RTG HDL files and Amiga driver code.

https://github.com/FPGAArcade/amiga_code
https://github.com/FPGAArcade/replay_amiga

This uses some primitives in replay_common. This is just a code dump to support the other projects while we faff around.
I think it makes sense you reuse my code rather than do it from scratch.

I'm still working to get a huge amout of stuff released incuding support for the Arduino Vidor and Replay1 board.
Work progresses rapidly on Replay2 which is XIlinx Ultrascale MPSoC based and we will support the hardmac GPU from the Amiga hopefully.

Note, you don't need the blitter file (vbe) which may be harder to integrate. Blitter support can be disabled in the driver.

The M68K CPU (TG68K variant) will follow shortly which has all the cas2/cmp2 stuff implemented as well.
Travelling this week so response will be intermittenent. Use the fpgaarcade forum if you want to get my attention.
Cheers,
Mike
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Re: Minimig RTG possible?

Post by Lroby74 »

fpgaarcade wrote:Hi all.
We've released our RTG HDL files and Amiga driver code.

https://github.com/FPGAArcade/amiga_code
https://github.com/FPGAArcade/replay_amiga

This uses some primitives in replay_common. This is just a code dump to support the other projects while we faff around.
I think it makes sense you reuse my code rather than do it from scratch.

I'm still working to get a huge amout of stuff released incuding support for the Arduino Vidor and Replay1 board.
Work progresses rapidly on Replay2 which is XIlinx Ultrascale MPSoC based and we will support the hardmac GPU from the Amiga hopefully.

Note, you don't need the blitter file (vbe) which may be harder to integrate. Blitter support can be disabled in the driver.

The M68K CPU (TG68K variant) will follow shortly which has all the cas2/cmp2 stuff implemented as well.
Travelling this week so response will be intermittenent. Use the fpgaarcade forum if you want to get my attention.
Cheers,
Mike
It's wonderfull, thank you!!
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Re: Minimig RTG possible?

Post by Sorgelig »

fpgaarcade wrote:Hi all.
We've released our RTG HDL files and Amiga driver code.

https://github.com/FPGAArcade/amiga_code
https://github.com/FPGAArcade/replay_amiga

This uses some primitives in replay_common. This is just a code dump to support the other projects while we faff around.
I think it makes sense you reuse my code rather than do it from scratch.

I'm still working to get a huge amout of stuff released incuding support for the Arduino Vidor and Replay1 board.
Work progresses rapidly on Replay2 which is XIlinx Ultrascale MPSoC based and we will support the hardmac GPU from the Amiga hopefully.

Note, you don't need the blitter file (vbe) which may be harder to integrate. Blitter support can be disabled in the driver.

The M68K CPU (TG68K variant) will follow shortly which has all the cas2/cmp2 stuff implemented as well.
Travelling this week so response will be intermittenent. Use the fpgaarcade forum if you want to get my attention.
Cheers,
Mike
Thanks for sharing the code!
Although RTG is nice to have it's something which can be added later. Actually For MiSTer the HDL part probably has to be modified very much or even must be rewritten from scratch by using only registers part. MiSTer doesn't need rendering part as it can be done directly from memory by internal scaler.
M68K would be more helpful though.. Hope it won't take another year to release.
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Re: Minimig RTG possible?

Post by ex68k »

Thanks for sharing the code!
Although RTG is nice to have it's something which can be added later. Actually For MiSTer the HDL part probably has to be modified very much or even must be rewritten from scratch by using only registers part. MiSTer doesn't need rendering part as it can be done directly from memory by internal scaler.
M68K would be more helpful though.. Hope it won't take another year to release.
Really? We were waiting for this a long time, and you don't care?
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Re: Minimig RTG possible?

Post by Sorgelig »

ex68k wrote:
Thanks for sharing the code!
Although RTG is nice to have it's something which can be added later. Actually For MiSTer the HDL part probably has to be modified very much or even must be rewritten from scratch by using only registers part. MiSTer doesn't need rendering part as it can be done directly from memory by internal scaler.
M68K would be more helpful though.. Hope it won't take another year to release.
Really? We were waiting for this a long time, and you don't care?
It's open source. You can help with development if you care so much.
Minimig has stability problem which is more important to fix.
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Re: Minimig RTG possible?

Post by fpgaarcade »

The software driver is the most useful to you I would imagine, the RTL can be stripped down - the blitter, sprite etc are all optional.

The RTG memory interface bolts onto a second read only channel to my memory controller.

If you don't have enough bandwidth from the SDRAM, it should be trivial to add it to the PS side - I assume the core can already do write access to the DDR3? You then mux the Amiga chipset output with the RTG according to the select output.

For the ultrascale I am moving to the PS side which has more memory bandwidth and I can integrate the GPU into the output path.
/Mike
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Re: Minimig RTG possible?

Post by kolla »

ex68k wrote:
Really? We were waiting for this a long time, and you don't care?
We were? I was not.

Once you go RTG (and RTA, that is AHI), you are abandoning the reason for going with FPGA in the first place - the Amiga chipset. I much rather have improved AGA, even beyond what “real” Amiga hardware can do, like more chipram and perhaps a “turbo mode” where animating in HAM8 modes with DPaint becomes more bearable :)

“Most wanted” for me though, is an ethernet device, that shows up as a tap device on the linux side.
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Re: Minimig RTG possible?

Post by fpgaarcade »

we've released our Ethernet driver as well btw.
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Re: Minimig RTG possible?

Post by Sorgelig »

fpgaarcade wrote:The software driver is the most useful to you I would imagine, the RTL can be stripped down - the blitter, sprite etc are all optional.

The RTG memory interface bolts onto a second read only channel to my memory controller.

If you don't have enough bandwidth from the SDRAM, it should be trivial to add it to the PS side - I assume the core can already do write access to the DDR3? You then mux the Amiga chipset output with the RTG according to the select output.

For the ultrascale I am moving to the PS side which has more memory bandwidth and I can integrate the GPU into the output path.
/Mike
Minimig on MiSTer uses DDR3. RTG will be just another memory region in DDR3. Rendering part is not required, it can be directly output by scaler as from frame buffer.
But as i've told, right now for me stability is more important. Although anyone else can port RTG code to MiSTer's Minimig. I simply have no time for this right now.
Ethernet sounds good. This actually is more important than RTG. I need to check the code to see how portable it is.
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Re: Minimig RTG possible?

Post by Sorgelig »

I don't see HDL code for Ethernet. Has it been released?
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Re: Minimig RTG possible?

Post by Sorgelig »

Oh, i see M68K has been released!
Thanks!
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Re: Minimig RTG possible?

Post by fpgaarcade »

I pushed it out so Tobiflex could have a look, but it has a glitch in 68000 mode. I'm backporting a regression test and will attempt a fix today.
I think we'll merge into Tobiflex's master repos but I may maintain my variant as I've been working on a 32 bit and pipelined version.
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Re: Minimig RTG possible?

Post by fpgaarcade »

The Ethernet RTL is in my 68060 bridge. I see no reason not to release it shortly, but all it does is connect the processor to the MAC chip. There is little RTL involved.
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Re: Minimig RTG possible?

Post by fpgaarcade »

If you are using the PS DDR3 that much have a long latency? Can you get a read back in a single 68000 cycle without stalling the CPU?
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Re: Minimig RTG possible?

Post by Sorgelig »

fpgaarcade wrote:I pushed it out so Tobiflex could have a look, but it has a glitch in 68000 mode. I'm backporting a regression test and will attempt a fix today.
I think we'll merge into Tobiflex's master repos but I may maintain my variant as I've been working on a 32 bit and pipelined version.
Oh, i see.. So i need to wait for fix then.
Is there improvements for Fmax since tg68k?
Could you do something with RAM_LUT entity? It would be good to keep m68k self-contained without additional libraries. I'm not very familiar with VHDL specifics, but even if i add if ... generate around RAM_LUT use, Quartus still complain that RAM_LUT is missing, even if generate block has false condition. What's the point for RAM_LUT instead of simple inferred RAM?
fpgaarcade wrote:The Ethernet RTL is in my 68060 bridge. I see no reason not to release it shortly, but all it does is connect the processor to the MAC chip. There is little RTL involved.
oh, i see.. So it's most likely won't work.
I was thinking to make virtual HDD from linux folder like in UAE. Actually there is no much use for internet connection on Amiga. It's more about file transferring.
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Re: Minimig RTG possible?

Post by fpgaarcade »

I hope to fix it today.
You just need to include the RAM_LUT in my common lib into your project as well as the M68K files.

The RAM primitives map to Xilinx elements well and I can apply constraints. I have different prims for different architectures, that's a generic one.
It gives me target abstraction,but also performance where needed.
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Re: Minimig RTG possible?

Post by Sorgelig »

fpgaarcade wrote:I hope to fix it today.
You just need to include the RAM_LUT in my common lib into your project as well as the M68K files.

The RAM primitives map to Xilinx elements well and I can apply constraints. I have different prims for different architectures, that's a generic one.
It gives me target abstraction,but also performance where needed.
what's the behavior of RAM_LUT? Does it need 1/2 cycles of delay the data output or immediate availability?
If i unblock original regfile() will it work? Did you test it?
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Re: Minimig RTG possible?

Post by Sorgelig »

fpgaarcade wrote:If you are using the PS DDR3 that much have a long latency? Can you get a read back in a single 68000 cycle without stalling the CPU?
Of course no, if you mean a random address read. But with cache it works pretty much fast. Even a little faster than SDR SDRAM.
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Re: Minimig RTG possible?

Post by fpgaarcade »

"Of course no, if you mean a random address read"
ok, then you cannot accurately emulate a stock machine then :(

You should aim to make no modifications to the code otherwise you will always be merging.

Just add the two files from the lib
https://github.com/FPGAArcade/replay_co ... _lib/prims
and the replay base package file
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Re: Minimig RTG possible?

Post by Sorgelig »

What's the problem with 68000 btw?

I think i will just make my own RAM_LUT, so will be able to use m68k as-is. Currently i use regfile for testing purpose.
Can you clean the source from warnings of "assigned but not used" and "already in sensitivity list"..
I usually fix it first, so i won't miss some important warnings later.

Can you tell more about m68k improvements over tg68k? All 020 instructions are properly implemented?
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Re: Minimig RTG possible?

Post by Sorgelig »

fpgaarcade wrote:ok, then you cannot accurately emulate a stock machine then
ChipRAM is in SDRAM, so it's cycle accurate.
FastRAM (and later RTG) is in DDR3. FastRAM is not included in "stock" machine. It's part of accelerator where performance varies from accel to accel.
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Re: Minimig RTG possible?

Post by fpgaarcade »

Sorgelig wrote:
fpgaarcade wrote:ok, then you cannot accurately emulate a stock machine then
ChipRAM is in SDRAM, so it's cycle accurate.
FastRAM (and later RTG) is in DDR3. FastRAM is not included in "stock" machine. It's part of accelerator where performance varies from accel to accel.
sure that's fine. Consider the M68K a pre-release at the moment.
"assigned but not used" this is normal and not an issue. Either debug or signals will be used later.
"already in sensitivity list".. this will be fixed.
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Re: Minimig RTG possible?

Post by Sorgelig »

this part is not verilog portable:

Code: Select all

    g_xil_regfile       : in   boolean := true -- set for xilinx prims on regfile
Consider to change to this:

Code: Select all

    g_xil_regfile       : integer := 1 -- set for xilinx prims on regfile
Locked

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