Seem to remember when looking at the datasheets it was possible to ignore the 6800 bus and basically drive the 6800 signals in sync with the 68000 bus and assert DTACK as usual. It's also used for autovector interruptrs or something (VMA?) but I think you can do a similar thing by placing the vector level on the bus and handling it differently. Sounds like a few lines of code and must have been done to get 020+ CPUs to work as they don't support 6800 bus.
Autovector is the problem, the 020 has the AVEC pin to emulate the 68xx cycles, but its not so easy on the 68000. However the 68SEC000 does have the AVEC pin and is wired much like how the 020 is done. That emulates and uses DTACK as you mention. That is proven stuff on the 020 so shouldn't take to long to adapt it for the SEC CPU. That SEC CPU claims up to 80MHz speeds, I maxed out the HC at 38MHz, so I need to move over to that SEC CPU anyway. So I have abandoned the 68HC000 stuff now.
Maybe forget the fast ROM and just load ROM into fast ram on startup. Isn#t there auto boot prgs to do that?
ROM is running at 32MHz anyway, the ROM decoding logic in the STE is pretty fast and with a 55nS ROM, it *just* manages to keep up before the CPU reads DTACK on S4. So loading into fast-ram (32MHz) isn't going to be any faster.
Sounds like you need to move to SDRAM to keep up with the CPU...
SRAM seems to be about 45ns, I am hoping to ramp up to 64MHz with the SEC CPU, but Likely after somewhere around 50MHz will have to start using waitstates, unless faster SRAM can be found. Though currently I am working at 32MHz for fast-ram as its a sensible point to work to now the HC stuff is proven to work up to those speeds.
As a side note, I may prototype my SRAM board with a adapter to fit my STE V1 booster. Then at least people can add it to the current series of booster, however I am not sure on the height between the booster and the shielding , so if anyone can look into that it would help me out.