Sharp X68000 Code

[Gehstock]

if someone search for a new Project
http://fpga8801.seesaa.net/category/247823249-1.html

[retrorepair]

Looks like it's currently active but since I don't read Japanese I can't tell how far along it is. Very, very interesting though!

[Estrayk]

Will be a dream a X68000 in the MIST.

[mfro]

Looks like it's currently active but since I don't read Japanese I can't tell how far along it is. Very, very interesting though!

At least it synthesizes without any error.

Might be a bit too heavy for the MiST, however. The core fills up 68% logic on a Cyclone V ...

[jotego]

It says they are working now on the floppy disk emulation.

[Gehstock]

Looks like it's currently active but since I don't read Japanese I can't tell how far along it is. Very, very interesting though!

At least it synthesizes without any error.

Might be a bit too heavy for the MiST, however. The core fills up 68% logic on a Cyclone V ...

[retrorepair]

That's very cool! Wonder if jotego's YM2151 would fit in there too?

[jaildesigner]

This core would be like a dream come true!

But I wonder what will happen with all the different refresh rates it can handle, I think it uses 15, 24 and 31Khz

[Newsdee]

I'll take whatever comes before thinking about extra features

[Sorgelig]

Use Revision F68k_DE0 needs some work but Fits

It doesn't. Not enough M9K memory blocks.

[Gehstock]

But we have SDRAM

[Sorgelig]

DE with Cyclone V has 3Mbit RAM(M10K). Our Cyclone III has 600KBit RAM(M9K). Actually not only total amount of bits important but total amount of blocks as well because blocks cannot be shared. Or FPGA has 66 blocks, while Cyc V has ~300 blocks.

Thus.. don't expect it ported. With such high graphics specs of X68000 i believe a lot of FPGA RAM used.

[Sorgelig]

FPGA RAM is more versatile. It's dual ported static RAM (SRAM) with much higher speed and zero latency. SDRAM need around 10 clock cycles to get the data. You can compare yourself.

[Sorgelig]

Don't want to let you down, but check X68000 hw.
It has 3 separate RAM systems:
1) main RAM up to 12MB - can emulate it with MiST SDRAM
2) 16KB SRAM - this is easy to emulate with FPGA RAM
3) VRAM: 1056 KB - here we have a problem. May be it's possible to emulate with MiST SDRAM if bandwidth is higher than sum of Main RAM and VRAM. But expect a lot of work here.

I'm not familiar with X68000. I think, that time the only RAM they could use is Asynchronous DRAM as a main RAM. It means you need around 10x times faster SDRAM to emulate Async DRAM (but since CPU doesn't access the RAM at every cycle, timings can be relaxed). I have no idea what they've used for VRAM. Probably also Async. DRAM.
When i was making SAM Coupe core i had similar problem because video buffer of SAM Coupe can be anywhere in the whole RAM. But since SAM Coupe has single RAM system shared on original HW, i had much more relaxed conditions.. With X68000 case, there are 2 separate RAM systems which will be much harder (if possible at all) to fit into single SDRAM chip.
Even Amiga has single RAM system - so don't compare it to X68000.

[Gehstock]

So I wrote that yes it still work needed, but Logic Cells we have enough. And Remember we have a Genesis-Beta-Core Now, nothing is Impossible.

[phoboz]

Thid should be a feasable project now for the MiSTer, since it also uses the Cyclone V FPGA?

[Sorgelig]

Yeah, FPGA in MiSTer is bigger than in FPGA where X68000 targeted.