PLEASE POST A CLEAN <=300K PIC IN JPG THE INSIDE OF YOUR ST

[Frank B]

Here's one of my STEs. I don't think we have a picture of this type yet. It has the integrated blitter and square DMA chip.
The machine was in a hell of a state when I bought it on ebay but simbo brought it back to life!

[insanity]

Here's one of my STEs. I don't think we have a picture of this type yet. It has the integrated blitter and square DMA chip.
The machine was in a hell of a state when I bought it on ebay but simbo brought it back to life!

Have added this Frank... but can't make out the number, I assume a 'C' is hidden under that component -
is it CA401177 - this right?

baz

[simbo]

yes is always CA revisions of board

or C^x. for chips ... ^ = other than

C seems to be ataris theme

[jokker]

Atari 520ST C07115 Rev 2


Atar Mega ST2 C100167-001 Rev 5.0

[Dio]

Hello chaps.

One more for your collection - I think you already have one heavily modded, this is original and a flash-less picture resized until it was just under the 300K limit:

PAL 520STFM, TOS 1.02, purchased 12/86 with single-sided internal drive.

I'll post one of my (very late, 4Q 88, well after some of the later boards were in use) C070789 rev D at some point soon too.

Bit of a request: I've a bit of a project going on, trying to work out some details about the various hardware revisions. These pics have supplied some really useful data, but the text on the chips is really hard to read on lots of them and with the Shifter Faraday cages usually shut I can't get the Shifter IDs or crystal freqs (and to get the latter a 300K pic is rarely sufficient). I have already found one crystal freq not mentioned on any of the schematics, though.

If anyone who posted a compressed small pic or with the Shifter box shut wanted to post one a bit bigger with the Shifter box open and maybe the retaining clips removed from the custom chips I'd be a happy man (personally I'm not fussed about the 300K limit; that 900K 1040STF picture on the wiki is fantastic, exactly what I'm looking for). If they've been in your posession since day 1, I'd also appreciate any data on the purchase date, territory and (if never changed) ROM version.

[Dio]

Double post, I'm a numpty.

[Dio]

This may help about knowing diverse revisions:

Hi there ppera. (since I can't PM, this will have to go here...)

You posted a couple of pictures of early 520STM revisions in this thread. I've a bit of a project going on with the various revisions of the ST hardware, and I noticed the Glue on these two 520STMs is a slightly different rev (-38 instead of -38A) compared to the various later STF/FM machines.

Did you have either or both of these machines? If so, do you know of any differences in behaviour between this particular model and others? In particular, I'm interested to determine which Glue revision changed the PAL top border timing from early to late. The even earlier ST in this thread has a different Glue revision (-20) and so it might be that one, but I'm looking to rule the -38 in or out if I can.

Glad of any info you (or anyone else) can offer me.

Cheers
Dave

[insanity]

jokker and Dio,

Have added your motherboards to the wiki - Thanks!

Dio,

Ppera left the forum years back, so I would expect any reply - Sorry!

Cheers!

baz

[Dio]

OK, cheers.

[Dio]

You've put the wrong MB ID in the left column for mine .

[wongck]

Ppera left the forum years back, so I would expect any reply - Sorry!

But SofiST may make a reply

[wongck]

Edit:
duh... Hey double post as well & no delete post button.

[DarkLord]

Hadn't seen too much STacy stuff so here is my STacy's motherboard, with the
internal P/S and TOS ROM/memory board still plugged in. You can also see a
few of the wires from the HD floppy drive mod I'm working on.

This motherboard is marked:

STACY MAIN
C103999 - 001 Rev. B

P9070009.JPG

[ijor]

In particular, I'm interested to determine which Glue revision changed the PAL top border timing from early to late. The even earlier ST in this thread has a different Glue revision (-20) and so it might be that one, but I'm looking to rule the -38 in or out if I can.

I believe this changed between GLUE -38 and -38A. But I'm not so familiar with GLUE -20 revision. Those -20 parts are quite rare and even strange.

If somebody has any of those -20 revision chips, and is willing to part them for reverse engineering purposes, please drop me a PM.

[Dio]

Thanks - I've just aquired an old STM that should have a -38 chip in so I shall check that and report back.

I've already asked Jokker the exact same question on those -20s . Looking at that old machine of his with the -20 and the kludge on the ras / cas lines it looks like some patches might be needed though...

Because all the chips turned from -20 to -38 at the same time (and it's almost impossible that they all needed the same number of design revisions) it seems unlikely that suffix is a pure revision number, one guess would be that the -20 denotes 'preproduction' and -38 'production', or there's maybe something more subtle, like a change of silicon process. It may be that the second code (e.g PH023-020 on the DMA) denotes the revision, but they've been harder to read on the pictures so far (hence my desire to see more big pics with the Faraday cage open).

One of the things that's intriguing me most is that given the reported difficulties making border removals work on a very wide range of STs - always allegedly because Atari made lots of changes to Glue, MMU and Shifter - there seem to be very few revisions. There's some evidence for concluding that the actual chip logic didn't change from the STFM through to the advent of the STE.

My current theory is that the major differences in timing are to do with the large different master crystals and the presence or absence of the clock nudger - there are far more varieties there than there are in the custom chips.

(Problem is, to investigate that properly I need to start looking at things like getting STs from the US with the NTSC crystals. Ho hum...)

[ijor]

Hi Dio,

Looking at that old machine of his with the -20 and the kludge on the ras / cas lines it looks like some patches might be needed though...

That is not a problem. If you happen find any of the -20 chips, I would take care of them.

Because all the chips turned from -20 to -38 at the same time (and it's almost impossible that they all needed the same number of design revisions) it seems unlikely that suffix is a pure revision number ...

It is a revision code, not exactly a consecutive number. Why they used -20, and then they sort of "jumped" to -38, I have no idea. But it doesn't suprise so much, I've seen other cases like this. It is possible that there is a process difference. But again, I can't say too much about those "-20" chips.

One of the things that's intriguing me most is that given the reported difficulties making border removals work on a very wide range of STs - always allegedly because Atari made lots of changes to Glue, MMU and Shifter - there seem to be very few revisions. ... My current theory is that the major differences in timing are to do with the large different master crystals and the presence or absence of the clock nudger

I agree that there aren't so many versions of the chipset. I was saying something similar long ago. I think the main problem related to overscan coding was wake-ups. Not only that the different wakeups introduce more timing variations, the whole thing wasn't well understood (it was actually barely known) at the time. Main clock frequency is a minor issue. But yes, we know that some demos break on some (mostly rare ones) crystals. Not sure what you mean by "clock nudger" ?

[jokker]

I noticed the discussion and figured I'd reply to here...

I still have those chips Dio and I can send them to you if want to check them out. I certainly have no issues contributing back to this community!

Just PM me an address and I can mail them off (and package them up safely!)

I have enough spare ST's that I can get by without having the spares at all. Plus if they serve the greater good as a research tool, heck I'm all for it.

Guess I'd better take photo's of the rest of my ST's someday soon. Got another 520 modded to 1meg, a 1040, 2 more Mega ST4's and a Mega STE.

[Dio]

I agree that there aren't so many versions of the chipset. I was saying something similar long ago. I think the main problem related to overscan coding was wake-ups. Not only that the different wakeups introduce more timing variations, the whole thing wasn't well understood (it was actually barely known) at the time. Main clock frequency is a minor issue. But yes, we know that some demos break on some (mostly rare ones) crystals. Not sure what you mean by "clock nudger" ?

The clock nudger is the circuit present on STMs that tweaks the master clock based on the colour clock. I'm certain that it's purpose is to create a phase relation with the colour clock to avoid the dot crawl issue that affected the Spectrum (it used a different crystal for the colour clock and master clock, which is prohibited by the PAL / NTSC standards). I'm not exactly certain how it works, though, and I'm still investigating if it produces any detectable behaviour change in the system.

Hence also the NTSC STE's relatively large clock frequency jump, because they could save some money by making the master crystal 9 times that of the colour clock and eliminating the nudger. (I think you postulated in the past that the big clock frequency change explains the "MFP latency change" that the Alive overscan document suggests, I completely agree with you there).

If there's anyone who understands the 'nudger' circuit very well or is an electronics expert I'd love to see a good writeup. I'm only a dabbler at the wires and transistors level and I even then haven't been able to investigate it in detail yet (I only have a logic analyser rather than a full scope).

I in turn are slightly confused by the use of the term "wake-ups" - what do you mean by those?

[Dio]

I still have those chips Dio and I can send them to you if want to check them out. I certainly have no issues contributing back to this community!

Just PM me an address and I can mail them off (and package them up safely!)

You sir are a gent. I'm not sure if it's more valuable for you to send them to ijor or myself though. It is probably worth multiple people having a look in order that we can cross-check our conclusions?

[Dio]

Had a think about this overnight. I'm also very interested in that early motherboard in order to work out what the kludge is and hence if it's required for the early chip.

Would it be possible for me to have the motherboard & chips, and I can then have a look at them and pass either just the chips or the board too onto ijor later?

I would be happy to put up some money as well as postage costs. And I don't know if the ST scene has completionist collectors, but one could value it highly - so I'd also be quite clear that it won't be sold on.

[ijor]

The clock nudger is the circuit present on STMs that tweaks the master clock based on the colour clock...

I'm not expert in this kind of circuits. But as far as I understand, this is some sort of PLL like circuit for locking HSYNC to the color clock. It will, of course, affect the master clock. But I don't think this will be very significant for our purposes.

(I think you postulated in the past that the big clock frequency change explains the "MFP latency change" that the Alive overscan document suggests

Yeah, I forgot about that. Guess I'm getting older ...

I in turn are slightly confused by the use of the term "wake-ups" - what do you mean by those?

Oh, now is you the one who seems to be getting older Because I'm (almost) sure we talked about this, at least, once.

Wakeups refer to the different phase relationships between the GLUE video process, and the MMU DRAM process. The relationship is established at power-up time and is not affected by reset. But it could change across different power-up cycles on the very same machine. Hence the term "wake-up".

I'm also very interested in that early motherboard in order to work out what the kludge is and hence if it's required for the early chip.

I don't mind at all you checking it first. But I'm not sure it is correct to abuse the generosity of jokker. I don't need (and I don't want) the motherboard, just the chipset. Do note that I won't be able to pass the chips later to you. They will be destroyed as part of the analysis process that I intend to perform.

What kludge are you talking about? I suspect you are looking at the wrong motherboard.

[DrCoolZic]

I in turn are slightly confused by the use of the term "wake-ups" - what do you mean by those?

Oh, now is you the one who seems to be getting older Because I'm (almost) sure we talked about this, at least, once.

Wakeups refer to the different phase relationships between the GLUE video process, and the MMU DRAM process. The relationship is established at power-up time and is not affected by reset. But it could change across different power-up cycles on the very same machine. Hence the term "wake-up".

Correct! If I remember correctly you even provided a program for that

[Dio]

I in turn are slightly confused by the use of the term "wake-ups" - what do you mean by those?

Oh, now is you the one who seems to be getting older Because I'm (almost) sure we talked about this, at least, once.

Wakeups refer to the different phase relationships between the GLUE video process, and the MMU DRAM process. The relationship is established at power-up time and is not affected by reset. But it could change across different power-up cycles on the very same machine. Hence the term "wake-up".

Ah, right. Yes, I remember that discussion, although I don't remember used the term for it at that point.

I've been doing some investigations to try to observe this and I haven't yet been able to do from software on the two FMs I've tested to this point. The logic analyser timing looks exactly the same too, but that's only on the one board though so far. Could be that this machine has a very strong tendency to boot up in the same phase. In the meantime I'm 'simply' trying to determine the video details in as much detail as possible so if it ever does happen I'm more likely to see it.

So far I can see one timing window that could easily move; the relative time at which the Glue shadows writes to $FF8260 vs. when the Shifter receives it through the bus gateway (the Glue can see it at least one CPU cycle earlier because it's on the CPU bus). I haven't analysed that under stress conditions yet though; I'm examining the LOAD / DE behaviour in detail first. Because it's a shadowed write, I need to understand any possible effects, since there's no actual bus response to it.

Do you have a link to the source for the detection program DrCoolZic mentioned, or could you describe the criteria that were used to detect the change?

But I'm not sure it is correct to abuse the generosity of jokker.

Absolutely. Even offering the chips is undoubtedly a generous act.

I don't need (and I don't want) the motherboard, just the chipset. Do note that I won't be able to pass the chips later to you. They will be destroyed as part of the analysis process that I intend to perform.

I definitely don't plan to destroy the chips - just sub them in another board and run the logic analyser on the system and my library of chip testers on the machine to check for any differences in timing. If I was taking a belt-and-braces approach I'd like to verify the pinout hadn't changed to verify there's no danger from doing this, although I view that as unlikely. Of course, it's possible that they simply just won't function in a later motherboard.

What kludge are you talking about? I suspect you are looking at the wrong motherboard.

Err - looking again, yes. OK, so the motherboard is not relevant, if I don't bother to check the pinout.

Irritatingly, the STM I picked up at the weekend turns out to have the -38A in - it's actually a few months older than my early STFM - so I still don't have a -38 Glue to compare against. Back to eBay I go... at least I think I have divined enough about how the serial numbers work to be reasonably sure I can ask an informed question and know what chip is inside it.

We may, just possibly, be a bit off-topic here .

[Dio]

Anyway, back on topic:

PAL 520STM, thought to be original. Looks to have been made in early to mid 1987 - sticker (Silica Shop? My STFM had the same type) on the bottom said 12/87 so it may have sat in inventory for a bit.


PAL 520STFM, late 87. Not quite original; has a yellow/green LED keyboard but a red/red top cover, and the drive hole has been filed around, so presumably was SS and swapped to DS. Doesn't look to have any mods though.


PAL 520STFM. Serial number indicates 1988 or 89 - surprisingly late for this board layout, the custom chips have the iMP logo. Ribbon cables are for the half meg RAM expansion. Floppy drive looks to be original and is DS.

[Nyh]

A TT 030 Rev H