TomH wrote:Especially as I think you've already been extremely helpful, and evidently I haven't been the best at asking questions, I'm hoping that a more thorough search of this forum's archives is going to throw some light on things.
I think I understand your questions, and I think I answered them already. But here I'll try to elaborate again ...
What is the delay, and how many cycles take from the test to the actual signal's edge?
As I said, there is no strict answer, and, from a software point of view, you probably don't really care. There is no strict precise cycle that can be defined as when the test and the comparison is performed. Hardware doesn't work like that, it has pipeline and internal delays. Furthermore, when the CPU performs a write, a bus cycle takes four clock cycles. So which one of these four clocks is the cycle that the write is being performed?
What matters is the relation, the relative distance from one test/comparison to the other. This matter because this give you the line length. And the answer to this is obvious and trivial. E.g., for a normal 50Hz line that, according to the table, starts at cycle 56 and ends at cycle 376. The width of the DE pulse is simply, and obviously, 376 - 56 = 320 cycles. This is valid for all cases, except
, for our LINE-50 entry which is a very special case ...
Are the H and DE signal activated simultaneously at LINE-50?
Once again, this is a very special case because here DE is affected only indirectly. There is no test at this point to change the DE state at all. The only test at this point is for asserting HSYNC. What happens is that whenever HSYNC is asserted, DE is deasserted after a synchronous delay. This happens no matter the resolution or the previous value of the horizontal counter.
For the purpose of computing the line length, the DE timing here is as if there was an extra delay of two cycles. You consider then DE to be disabled at LINE-48. This gives you the full screen line length = LINE-48-4 = 512-52 = 460 cycles.
And once again, the absolute cycle numbers on the table are just a convention. They don't have any real meaning and I honestly don't even know their origin. But I trust Troed that this was the convention used by most programmers.