YM access timing

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Foxie
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YM access timing

Post by Foxie »

On the STFM, it looks like an access to the YM chip takes 8 clock cycles at 8MHz. However, as far as I understand it's actually less than 8 clock cycles (an odd number) and is rounded up to the nearest four when running in ST RAM.

If you have a Falcon with CT60, what's the fastest access you can do to the chip? Every five 8MHz clock cycles? Every seven? Is that the same on the TT with fast RAM? Or does it still round up to 8 cycles?
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Re: YM access timing

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Re: YM access timing

Post by Foxie »

I was looking at that thread, but I'm still not completely sure. Does that mean a YM access is always exactly five 8MHz cycles on ST/TT/Falcon? And I assume on an accelerated Falcon no rounding up by four will occur?

What I'm trying to determine is how fast an I/O port pin can be toggled. I imagine if you don't have any rounding or instruction fetching overhead, the period will be about 1.25us (two accesses of five 8 MHz cycles).
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Re: YM access timing

Post by ijor »

Foxie wrote:I was looking at that thread, but I'm still not completely sure. Does that mean a YM access is always exactly five 8MHz cycles on ST/TT/Falcon? And I assume on an accelerated Falcon no rounding up by four will occur?

What I'm trying to determine is how fast an I/O port pin can be toggled. I imagine if you don't have any rounding or instruction fetching overhead, the period will be about 1.25us (two accesses of five 8 MHz cycles).
I'm not familiar with the TT or the Falcon. In the ST an YM access will be five cycles minimum. If there is no rounding up (say, running from ROM or fast RAM) and no DMA taking bus ownership, then yes, it would be exactly 5 cycles. And if you somehow can avoid all processor overhead, then you could indeed write to the PSG every 5 cycles.
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Re: YM access timing

Post by Foxie »

ijor wrote: I'm not familiar with the TT or the Falcon. In the ST an YM access will be five cycles minimum. If there is no rounding up (say, running from ROM or fast RAM) and no DMA taking bus ownership, then yes, it would be exactly 5 cycles. And if you somehow can avoid all processor overhead, then you could indeed write to the PSG every 5 cycles.
Thanks, this is what I was looking for. I needed to figure out the worst-case strobe pulse width on the printer port, and data setup time. I figure you always need two accesses to the YM to change from writing data to bringing strobe low. So I think the setup time will be 1.25us worst-case, and the strobe pulse 625ns. Should be enough to allow for a couple of metres of cable.
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