Keyboard controller

tobe · Post by **tobe** » Tue Dec 21, 2004 12:29 pm

Hi,

It is possible to upload and execute code in the keyboard controller via the ACIA ?

It is possible to re-code the controllers ? I mean joystick for example ?

Thanks

Post by **simonsunnyboy** » Tue Dec 21, 2004 1:17 pm

Afaik it is not possible. The ACIA is some microcontroller with only 128 bytes of RAM or so. It wouldn't be of much use anyway as the ACIA is only connected via a slow serial link so if you could manage to upload code, it couldn't supplement the m68k that much as all your results would had to pass the slow serial link.
Anyway what do you want to change? All the ACIA does is preparing status packets each a couples of bytes long and sending them back to the ST. The rest is just a small interrupt that takes these packets and stores the contents in a place where you want to access them.

tobe · Post by **tobe** » Tue Dec 21, 2004 1:27 pm

First, I want to know if i can code something for the keyboard controller (the 6301 processor), just for fun

Also, it seems possible to rewrite (and improve) the joystick & keyboard management, quite interresting !

Post by **simonsunnyboy** » Tue Dec 21, 2004 1:54 pm

Well the current code is placed into ROM so you would need to replace that. And afaik it is not possible to execute code from the limited amount of RAM (Harvard architecture like all decent mcus have, mainly means there is a difference between memory for code and your data). Good luck but I doubt you can utilize the 6301 for anything useful in the ST. A standalone 6301 is ofcourse different but then you could use a modern mcu like an Atmel AVR of a Microchip PIC.

BTW. I had a chat with the Paranoid about this at Paracon - and he fully agreed on my opinion expressed here and in the post before. The famous ULM chitchat on the IKBD is a fake and it does not work!

Post by **ijor** » Tue Dec 21, 2004 2:15 pm

tobe wrote:It is possible to upload and execute code in the keyboard controller via the ACIA ?

Yes. Not only is possible, it has been done already. But it is not easy at all ...

It is possible to re-code the controllers ? I mean joystick for example ?

Digital Joysticks as ST ones are simple devices, so this won't be too difficult. Handling keyboard and/or mouse is much more complicated.

As Simon said, the IKBD MCU has 128 bytes of RAM only. It requires quite some trickery to upload and execute code.

simonsunnyboy wrote:The ACIA is some microcontroller ... Anyway what do you want to change? ... Harvard architecture

Just for the record, the ACIA is not the keyboard controller. It is just the serial UART that connects it to the main 68k CPU. The MCU is an HD6301, a Motorola 6800/6801 derivate.

It doesn't have Harvard atchitecture, but this is not very relevant here. The limitation is the physical amount of RAM, not the address space of the number of address lines.

Uploading code to the IKBD was done for two reasons, afaik. For protections, and for using IKBD without ACIA interrupts.

Post by **simonsunnyboy** » Tue Dec 21, 2004 5:01 pm

Ok thanks for pointing out that I was confusing the ACIA and the IKBD - sorry for that, I should have known better!
Beside that I think the communications problems and the RAM size are still the limiting factors!
Cosidering the joysticks all you need are two bytes with bits for switches set - the IKBD does that. I can't think what to optimize there.

tobe · Post by **tobe** » Wed Dec 22, 2004 3:06 pm

The 6800 and derivates are nice toys for coders

ijor wrote:Uploading code to the IKBD was done for two reasons, afaik. For protections, and for using IKBD without ACIA interrupts.

Nice ! Nice !
At first I would like to try to compute curves for effects, just for the fun, no real needs or optimisations here

Then, using IKBD without interrupts is quite interresting, i've heard it was done in a demo for the menu screen.

I'm going to try to understand how the 6301 and the 68000 communicate with the ACIA controller.

Post by **Mug UK** » Wed Dec 22, 2004 3:25 pm

Was mentioned on dBug site in the interview with Andy The Arfling from the BBC that he coded a protection system in the ACIA.

Cyrano Jones · Post by **Cyrano Jones** » Thu Dec 23, 2004 8:31 am

Yep, from what I remember it was generating a timesync'd seed value we were using for the other shells to use as part of a decryption key.

Must dig that source out and post it someday. Especially liked my part that basically ran code from the pallette registers in the ROM ($ffff8240.w) (yes - even with the high bits being junked on a standard STfm

) as no reset cart saved the pallette

(Even if Zippy did keep on cracking it hehehehe - but then I cracked the shell he did so thats ok too

)

tobe · Post by **tobe** » Thu Dec 23, 2004 10:11 am

From the pallette registers

I am very interested by your sources !

Grazey / PHF · Post by **Grazey / PHF** » Thu Dec 23, 2004 12:37 pm

CJ, I think IÃ¢Â€Â™ve still got those sources (Synclok?)

If so, I can post them if you give the nodÃ¢Â€Â¦

Grz

tobe · Post by **tobe** » Thu Dec 23, 2004 3:04 pm

There's a nice tutorial on 6301 in the STMAGS 53 & 55 !

Thanks GT 'Poulpi' Turbo

Cyrano Jones · Post by **Cyrano Jones** » Thu Dec 23, 2004 3:35 pm

Grazey / PHF wrote:CJ, I think IÃ¢Â€Â™ve still got those sources (Synclok?)

If so, I can post them if you give the nodÃ¢Â€Â¦

Grz

Was thinking maybe a page about how it actually works... you've seen the code, it doesnt really explain itself well

Post by **ijor** » Thu Dec 23, 2004 3:36 pm

Cyrano Jones wrote:Yep, from what I remember it was generating a timesync'd seed value we were using for the other shells to use as part of a decryption key.

Must dig that source out and post it someday. Especially liked my part that basically ran code from the pallette registers in the ROM ($ffff8240.w) (yes - even with the high bits being junked on a standard STfm ) as no reset cart saved the pallette

Very nice CJ. Would be very interesting to see that source code.

Btw, I recently come across a protection thar runs code in the PSG (the sound chip). Specially wierd because the PSG is an 8-bit peripheral.

Cyrano Jones · Post by **Cyrano Jones** » Thu Dec 23, 2004 3:37 pm

tobe wrote:From the pallette registers

I am very interested by your sources !

Yes, a whole 19 bytes of code

(or was it 17?)

tobe · Post by **tobe** » Sun Dec 26, 2004 2:56 pm

The STMag tutorial is very interresting, it explain how to safely upload custom code in the 6301 and execute it.
I'm going to try this next year

tobe · Post by **tobe** » Wed Jan 05, 2005 5:10 pm

Here is the code source from STMag :

Code: Select all

* Programme de gestion
* clavier/joystick/souris
* Ecrit avec DevpacST 2
* (C) Stephane CATALA
* (Belzebub/ST Connexion)
* ST Magazine 1991

* Definition des Macros

Send Macro
	lea		\1(a6),a0
	moveq	#\1Len-1,d0
	btst	#1,$FFFFFC00.W
	beq.s	*-6
	IFEQ	'\2'-'+'
	move.b	(a0)+,$FFFFFC02.W
	dbra	d0,*-12
	ENDC
	IFEQ	'\2'-'-'
	move.b	0(a0,d0),$FFFFFC02.W
	dbra	d0,*-14
	ENDC
	ENDM

Print Macro
	move.w	#$2700,sr
	pea		\1(a6)
	move.w	#$9,-(a7)
	trap	#1
	addq.l	#6,a7
	move.w	#$2300,sr
	ENDM

* Mise en place de la routine Ikbd
	clr.l	-(a7)
	move.w	#$20,-(a7)
	trap	#1
	addq.l	#6,a7
	move.w	#$2700,sr
	lea		DataOffset(pc),a6
	Send	Boot,+
	Send	PauseOutput,+
	Send	ControllerExecute,+
	Send	Loader,-
	Send	Program,-
	
* Lancer Demonstration
	Lea		Vbl(pc),a0
	move.l	a0,$70.W
	clr.b	$FFFFFA07.W
	clr.b	$FFFFFA09.W
	move.w	#$2300,sr

Print6301Data
	Print	Home
	Lea		Data6301(a6),a5
	moveq	#3,d7
Read6301Data
	move.b	(a5)+,d0
	bsr		Ascii
	move.b	d1,Hexa+1(a6)
	Bsr		Ascii
	move.b	d1,Hexa(a6)
	Print	Hexa
	dbra	d7,Read6301Data
	bra		Print6301Data
	
Ascii
	move.b	d0,d1
	and.b	#$F,d1
	add.b	#'0',d1
	cmp.b	#'9',d1
	ble.s	Decimal
	add.b	#'A'-'0'-10,d1
Decimal
	lsr.w	#4,d0
	rts
	
Vbl
	move.w	#$2700,sr
	movem.l	d0/a0,-(a7)
Transmit
	btst	#1,$FFFFFC00.W
	beq		Transmit
	move.b	#4,$FFFFFC02.W
	lea		Data6301(a6),a0
	moveq	#3,d0
Input6301
	btst	#0,$FFFFFC00.W
	beq		Input6301
	move.b	$FFFFFC02.W,(a0)+
	dbra	d0,Input6301
	movem.l	(a7)+,d0/a0
	rte
	
* Donnees

DataOffset				Equ	*

Home					Equ	(*-DataOffset)
	dc.b	$1B,'H',0
Hexa					Equ	(*-DataOffset)
	dc.b	0,0,$A,$D,0

Data6301				Equ	(*-DataOffset)
	ds.b	4

PauseOutput				Equ	(*-DataOffset)
	dc.b	$13
PauseOutputLen			Equ	(*-DataOffset)-PauseOutput

ControllerExecute		Equ	(*-DataOffset)
	dc.b	$22,$00,$B1
ControllerExecuteLen	Equ	(*-DataOffset)-ControllerExecute

Boot					Equ	(*-DataOffset)
	dc.b	$20,$00,$B0,$0B
	dc.b	$B9+LoaderLen		* $B0
	dc.b	$0F					* $B1			sei
	dc.b	$9E,$AF				* $B2			lds		$AF
	dc.b	$DC,$11				* $B4	Ready	ldd		$11
	dc.b	$2A,$FC				* $B6			bpl		Ready
	dc.b	$37					* $B8			pshb
	dc.b	$20,$F9				* $B9			bra		Ready
BootLen					Equ	(*-DataOffset)-Boot

Loader					Equ	(*-DataOffset)
	dc.b	$00					* $BA			dc.b	$0
	dc.b	$DC,$B4				* $BB			ldd		$B4
	dc.b	$DD,$80				* $BD			std		$80
	dc.b	$DC,$B6				* $BF			ldd		$B6
	dc.b	$DD,$82				* $C1			std		$82
	dc.b	$DC,$B8				* $C3			ldd		$B8
	dc.b	$DD,$84				* $C5			std		$84
	dc.b	$86,$F9				* $C7			ldaa	#$F9
	dc.b	$97,$86				* $C9			staa	$86
	dc.b	$CC,$00,$01			* $CB			ldd		#$1
	dc.b	$DD,$00				* $CE			std		$0
	dc.b	$43					* $D0			nota
	dc.b	$53					* $D1			notb
	dc.b	$97,$04				* $D3			staa	$4
	dc.b	$54					* $D4			lsrb
	dc.b	$DD,$06				* $D5			std		$6
	dc.b	$86,$40				* $D7			ldaa	#$40
	dc.b	$DD,$0B				* $D9			std		$B
	dc.b	$8E,$00
	dc.b	ProgramLen+$85		* $DB			lds		#$85+ProgramLen
	dc.b	$7E,$00,$80			* $DE			jmp		$80
LoaderLen				Equ	(*-DataOffset)-Loader

Program					Equ	(*-DataOffset)
	dc.b	$0D
	dc.b	$FF,$FF,$FF,$FF
	dc.b	$FF,$FF,$FF,$FF
	dc.b	$FF,$FF,$FF,$FF
	dc.b	$FF
	dc.b	$8E,$00,$82			*		Ikbd	lds		#JoyPort
	dc.b	$33					*				pulb
	dc.b	$5A					*		KeySca	decb
	dc.b	$2A,$26				*				bpl		Key
	dc.b	$D7,$03				*				stab	$3
	dc.b	$D7,$05				*				stab	$5
	dc.b	$DC,$0B				*				ldd		KeyBit
	dc.b	$48					*				lsla
	dc.b	$89,$00				*				adca	#0
	dc.b	$5C					*				incb
	dc.b	$2A,$02				*				bpl		Ok
	dc.b	$30					*				tsx
	dc.b	$5F					*				clr.b
	dc.b	$DD,$0B				*		Ok		std		KeyBit
	dc.b	$2A,$08				*				bpl		GetKey
	dc.b	$09					*				dex
	dc.b	$DC,$06				*				ldd		$6
	dc.b	$05					*				lsld
	dc.b	$C9,$00				*				adcb	#0
	dc.b	$DD,$06				*				std		$6
	dc.b	$E6,$10				*		GetKey	ldab	$10
	dc.b	$D8,$02				*				eorb	$2
	dc.b	$D4,$0B				*				andb	KeyBit
	dc.b	$27,$06				*				beq		Mouse
	dc.b	$E8,$10				*				eorb	$10
	dc.b	$E7,$10				*				stab	$10
	dc.b	$D6,$0C				*		Key		ldab	KeyNumber
	dc.b	$37					*		Mouse	pshb
	dc.b	$5F					*				clrb
	dc.b	$D7,$03				*				stab	$3
	dc.b	$D7,$05				*				stab	$5
	dc.b	$86,$00				*				ldaa	#0
	dc.b	$16					*				tab
	dc.b	$C4,$0A				*				andb	#$A
	dc.b	$10					*				sba
	dc.b	$48					*				lsla
	dc.b	$54					*				lsrb
	dc.b	$1B					*				aba
	dc.b	$D6,$07				*				ldab	$7
	dc.b	$D7,$CA				*				stab	MousePort
	dc.b	$98,$CA				*				eora	MousePort
	dc.b	$C4,$F0				*				andb	#$F0
	dc.b	$D8,$03				*				eorb	$3
	dc.b	$37					*				pshb
	dc.b	$34					*				des
	dc.b	$33					*				pulb
	dc.b	$44					*				lsra
	dc.b	$C2,$00				*				sbcb	#0
	dc.b	$44					*				lsra
	dc.b	$C9,$00				*				adcb	#0
	dc.b	$37					*				pshb
	dc.b	$34					*				des
	dc.b	$33					*				pulb
	dc.b	$44					*				lsra
	dc.b	$C2,$00				*				sbcb	#0
	dc.b	$44					*				lsra
	dc.b	$C9,$00				*				adcb	#0
	dc.b	$37					*				pshb
	dc.b	$DC,$11				*				ldd		$11
	dc.b	$2A,$A1				*				bpl		Ikbd
	dc.b	$7B,$20,$11			*		Wait	bit		#$20,$11
	dc.b	$27,$FB				*				beq		Wait
	dc.b	$32					*				pula
	dc.b	$97,$13				*				staa	$13
	dc.b	$5A					*				decb
	dc.b	$26,$F5				*				bne		Wait
	dc.b	$20,$98				*				bra		KeyScan
ProgramLen			Equ	(*-DataOffset)-Program

I'm going to rewrite this, without macros and more comments.

tobe · Post by **tobe** » Wed Jan 05, 2005 5:13 pm

and the 6301 instruction set

Code: Select all

----------------------------------------------------------------
|                                                              |
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|                           Motorola                           |
|                                                              |
|              666      88888      000     X     X             |
|             6        8     8    0   0     X   X              |
|            6         8     8   0   0 0     X X               |
|            666666     88888    0  0  0      X                |
|            6     6   8     8   0 0   0     X X               |
|            6     6   8     8    0   0     X   X              |
|             66666     88888      000     X     X             |
|                                                              |
|     6800/1/2/3/8 MICROPROCESSOR Instruction Set Summary      |
|                                                              |
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|                           .......                            |
|                    .....................                     |
|                .......X.............X.......                 |
|              ........XXX...........XXX........               |
|            .........XXXXX.........XXXXX.........             |
|           .........XXXXXXX.......XXXXXXX.........            |
|          .........XXXXXXXXX.....XXXXXXXXX.........           |
|         .........XXXXXXXXXXX...XXXXXXXXXXX.........          |
|         ........XXXX.....XXXX.XXXX.....XXXX........          |
|         .......XXX.........XXXXX.........XXX.......          |
|         ......XX............XXX............XX......          |
|          ....X...............X...............X....           |
|           ..X.................................X..            |
|            .....................................             |
|              .................................               |
|                .............................                 |
|                     ...................                      |
|                           .......                            |
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|                                                              |
|                                                              |
|Written by     Jonathan Bowen                                 |
|               Programming Research Group                     |
|               Oxford University Computing Laboratory         |
|               8-11 Keble Road                                |
|               Oxford OX1 3QD                                 |
|               England                                        |
|                                                              |
|               Tel +44-865-273840                             |
|                                                              |
|Created        August 1981                                    |
|Updated        April 1985                                     |
|Issue          1.4                Copyright (C) J.P.Bowen 1985|
----------------------------------------------------------------
----------------------------------------------------------------
|Mnem. |Op|HINZVC|IEXD#R|Description              |Notes       |
|------+--+------+------+-------------------------+------------|
|ABA   |1B|*-****|X     |Add accumulators         |A=A+B       |
|ABX   |3A|------|X     |Add registers            |X=X+B      #|
|ADCr s|B9|*-****| XXXX |Add with Carry           |r=r+s+C     |
|ADDr s|BB|*-****| XXXX |Add                      |r=r+s       |
|ADDD s|F3|--****| XXX* |Add Double accumulator   |D=D+s      #|
|ANDr s|B4|--**0-| XXXX |Logical AND              |r=r&s       |
|ASL  d|78|--****| XX   |Arithmetic Shift Left    |d=d*2       |
|ASLr  |48|--****|X     |Arithmetic Shift Left    |r=r*2       |
|ASLD  |05|--****|X     |Arithmetic Shift Left    |D=D*2      #|
|ASR  d|77|--****| XX   |Arithmetic Shift Right   |d=d/2       |
|ASRr  |47|--****|X     |Arithmetic Shift Right   |r=r/2       |
|BCC  a|24|------|     X|Branch if Carry Clear    |If C=0      |
|BCS  a|25|------|     X|Branch if Carry Set      |If C=1      |
|BEQ  a|27|------|     X|Branch if Equal          |If Z=1      |
|BGE  a|2C|------|     X|Branch if Greater/Equal  |If NxV=0    |
|BGT  a|2E|------|     X|Branch if Greater Than   |If Zv{NxV}=0|
|BHI  a|22|------|     X|Branch if Higher         |If CvZ=0    |
|BHS  a|24|------|     X|Branch if Higher or Same |If C=0     #|
|BITr s|B5|--**0-| XXXX |Bit Test                 |r&s         |
|BLE  a|2F|------|     X|Branch if Less or Equal  |If Zv{NxV}=0|
|BLO  a|25|------|     X|Branch if Lower          |If C=1     #|
|BLS  a|23|------|     X|Branch if Lower or Same  |If CvZ=1    |
|BLT  a|2D|------|     X|Branch if Less Than      |If NxV=1    |
|BMI  a|2B|------|     X|Branch if Minus          |If N=1      |
|BNE  a|26|------|     X|Branch if Not Equal      |If Z=0      |
|BPL  a|2A|------|     X|Branch if Plus           |If N=0      |
|BRA  a|20|------|     X|Branch Always            |PC=a        |
|BRN  a|21|------|     X|Branch Never             |No op      #|
|BSR  a|8D|------|     X|Branch to Subroutine     |-[S]=PC,PC=a|
|BVC  a|28|------|     X|Branch if Overflow Clear |If V=0      |
|BVS  a|29|------|     X|Branch if Overflow Set   |If V=1      |
|CBA   |11|--****|X     |Compare accumulators     |A-B         |
|CLC   |0C|-----0|X     |Clear Carry              |C=0         |
|CLI   |0E|-0----|X     |Clear Interrupt Mask     |I=0         |
|CLR  d|7F|--0100| XX   |Clear                    |d=0         |
|CLRr  |4F|--0100|X     |Clear accumulator        |r=0         |
|CLV   |0A|----0-|X     |Clear Overflow           |V=0         |
|CMPr s|B1|--****| XXXX |Compare                  |r-s         |
|COM  d|63|--**01| XX   |Complement               |d=~d        |
|COMr  |43|--**01|X     |Complement accumulator   |r=~r        |
|CPX  s|BC|--****| XXX* |Compare Index Register   |X-s         |
|DAA   |19|--****|X     |Decimal Adjust Acc.      |A=BCD format|
|DEC  d|7A|--**?-| XX   |Decrement                |d=d-1       |
|DECr  |4A|--**?-|X     |Decrement accumulator    |r=r-1       |
|DES   |34|------|X     |Decrement Stack Pointer  |S=S-1       |
|DEX   |09|---*--|X     |Decrement Index Register |X=X-1       |
|EORr s|B8|--**0-| XXXX |Logical Exclusive OR     |r=rxs       |
|INC  d|7C|--**?-| XX   |Increment                |d=d+1       |
|INCr  |4C|--**?-|X     |Increment accumulator    |r=r+1       |
|INS   |31|------|X     |Increment Stack Pointer  |S=S+1       |
|INX   |08|---*--|X     |Increment Index Register |X=X+1       |
|JMP  d|7E|------| XX   |Jump                     |PC=d        |
|JSR  d|BD|------| XX   |Jump to Subroutine       |-[S]=PC,PC=d|
|LDAr s|B6|--**0-| XXXX |Load Accumulator         |r=s         |
|LDD  s|FC|--**0-| XXX* |Load Double accumulator  |D=s        #|
|LDS  s|BE|--**0-| XXX* |Load Stack Pointer       |S=s         |
|LDX  s|FE|--**0-| XXX* |Load Index Register      |X=s         |
|LSR  d|74|--0***| XX   |Logical Shift Right      |d=->{0,d,C} |
|LSRr  |44|--0***|X     |Logical Shift Right      |r=->{0,r,C} |
|LSRD  |04|--0***|X     |Logical Shift Right      |D=->{0,D,C}#|
|MUL   |3D|-----*|X     |Multiply                 |D=A*B      #|
|NEG  d|70|--****| XX   |Negate                   |d=-d        |
|NEGr  |40|--****|X     |Negate accumulator       |r=-r        |
|NOP   |01|------|X     |No Operation             |            |
|ORAr s|BA|--**0-| XXXX |Logical inclusive OR     |r=rvs       |
|PSHA  |36|------|X     |Push                     |-[S]=A      |
|PSHB  |37|------|X     |Push                     |-[S]=B      |
|PSHX  |3C|------|X     |Push Index Register      |-[S]=X     #|
|PULA  |32|------|X     |Pull                     |A=[S]+      |
|PULB  |33|------|X     |Pull                     |B=[S]+      |
|PULX  |38|------|X     |Pull Index Register      |X=[S]+     #|
|ROL  d|79|--**?*| XX   |Rotate Left              |d={C,d}<-   |
|ROLr  |49|--**?*|X     |Rotate Left accumulator  |r={C,r}<-   |
|ROR  d|76|--**?*| XX   |Rotate Right             |d=->{C,d}   |
|RORr  |46|--**?*|X     |Rotate Right accumulator |r=->{C,r}   |
|RTI   |3B|??????|X     |Return from Interrupt    |{regs}=[S]+ |
----------------------------------------------------------------
----------------------------------------------------------------
|Mnem. |Op|HINZVC|IEXD#R|Description              |Notes       |
|------+--+------+------+-+-----------------------+------------|
|RTS   |39|------|X     |Return from Subroutine   |PC=[S]+     |
|SBA   |10|--****|X     |Subtract accumulators    |A=A-B       |
|SBCr s|B2|--****| XXXX |Subtract with Carry      |r=r-s-C     |
|SEC   |0D|-----1|X     |Set Carry                |C=1         |
|SEI   |0F|-1----|X     |Set Interrupt Mask       |I=1         |
|SEV   |0B|----1-|X     |Set Overflow             |V=1         |
|STAr d|B7|--**0-| XXX  |Store Accumulator        |d=r         |
|STD  d|FD|--**0-| XXX  |Store Double accumulator |D=r        #|
|STS  d|BF|--**0-| XXX  |Store Stack Pointer      |d=S         |
|STX  d|FF|--**0-| XXX  |Store Index Register     |d=X         |
|SUBr s|B0|--****| XXXX |Subtract                 |r=r-s       |
|SUBD s|B3|--****| XXX* |Subtract Double acc.     |D=D-s      #|
|SWI   |3F|-1----|X     |Software Interrupt       |-[S]={regs} |
|TAB   |17|--**0-|X     |Transfer accumulators    |B=A         |
|TAP   |06|******|X     |Transfer to CCR          |P=A         |
|TBA   |17|--**0-|X     |Transfer accumulators    |A=B         |
|TPA   |07|------|X     |Transfer from CCR        |A=P         |
|TST  s|7D|--**00| XX   |Test                     |s           |
|TSTr  |4D|--**00|X     |Test accumulator         |r           |
|TSX   |30|------|X     |Transfer Stack Pointer   |X=S         |
|TXS   |35|------|X     |Transfer Index Register  |S=X         |
|WAI   |3E|-*----|X     |Wait for Interrupt       |-[S]={regs} |
|---------+------+------+--------------------------------------|
| CCR     |-*01? |      |Unaffected/affected/reset/set/unknown |
| H       |H     |      |Half carry (Bit 5)                    |
| I       | I    |      |Interrupt mask (Bit 4)                |
| N       |  N   |      |Negative (Bit 3)                      |
| Z       |   Z  |      |Zero (Bit 2)                          |
| V       |    V |      |Overflow (Bit 1)                      |
| C       |     C|      |Carry (Bit 0)                         |
|----------------+------+--------------------------------------|
| r              |I     |Inherent (r=A,Op=4XH, r=B,Op=5XH)     |
| nn,E           | E    |Extended (Op=E, ~s=e)                 |
| nn,X           |  X   |Index (Op=E-10H, ~s=e+1, JSR ~s=e-1)  |
| n,D            |   D  |Direct (Op=E-20H, ~s=e-1)             |
| #n             |    # |Immediate (8-bit, Op=E-30H, ~s=e-2)   |
| #nn            |    * |Immediate (16-bit, Op=E-30H, ~s=e-2)  |
| a              |     R|Relative (PC=PC+2+offset)             |
| r              |      |Inherent (r=A,Op=BXH, r=B,Op=FXH)     |
|-----------------------+--------------------------------------|
|DIRECT                 |Direct addressing mode                |
|EXTEND                 |Extended addressing mode              |
|FCB      n             |Form Constant Byte                    |
|FCC      'string'      |Form Constant Characters              |
|FDB      nn            |Form Double Byte                      |
|RMB      nn            |Reserve Memory Bytes                  |
|-----------------------+--------------------------------------|
| A                     |Accumulator A (8-bit, Op=BXH)         |
| B                     |Accumulator B (8-bit, Op=FXH)         |
| D                     |A and B combined (16-bit, A hi, B lo) |
| P                     |Condition Code Register (8-bit, CCR)  |
| PC                    |Program Counter (16-bit)              |
| S                     |Stack Pointer (16-bit)                |
| X                     |Index Register (16-bit)               |
|-----------------------+--------------------------------------|
| a                     |Relative address (-125 to +129)       |
| d                     |Destination                           |
| n                     |8-bit expression (0 to 255)           |
| nn                    |16-bit expression (0 to 65535)        |
| r                     |Accumulator register A or B           |
| s                     |Source                                |
| +  -                  |Addition/subtraction                  |
| *  /                  |Multiplication/division               |
| &  ~                  |Logical AND/NOT                       |
| v  x                  |Logical inclusive/exclusive OR        |
| <-  ->                |Rotate left/right                     |
| [ ]                   |Indirect addressing                   |
| [ ]+  -[ ]            |Indirect auto-increment/decrement     |
| { }                   |Combination of operands               |
| {regs}                |All registers {PC,X,A,B,P}            |
| #                     |Instruction not applicable to 6800/2  |
|-----------------------+--------------------------------------|
| FFF8H to FFF9H        |Hardware interrupt vector             |
| FFFAH to FFFBH        |SWI instruction interrupt vector      |
| FFFCH to FFFDH        |Non-maskable interrupt vector         |
| FFFEH to FFFFH        |Reset vector                          |
----------------------------------------------------------------

tobe · Post by **tobe** » Wed Jan 05, 2005 5:14 pm

and the memory mapping of course :

Code: Select all

$0000-$001F	Internal registers
$0080-$00FF	Internal RAM (128 bytes)
$F000-$FFFF	Internal ROM

I have french docs about the internal registers, i can traduct them if someone need it

Post by **ggn** » Thu Jan 06, 2005 4:34 pm

STMag was a diskzine, right?

Anyone knows where to download the issues????

/George

tobe · Post by **tobe** » Thu Jan 06, 2005 6:08 pm

ST Magazine is a french paper magazine, the best computer related mag i ever read !
It's still alive, and there's an english version, you can find it here :
http://stmagazine.org/welcome.htm

Now about the keyboard controller, i'm writing a small code (based on the code above) to upload an init func, run it, then overwrite it with user code and execute it.
This code will be fully documented, the 6301 code and the procedure too.
I'm trying to find more docs about the internal registers of the 6301 mapped in the range [$0000-$001F], anyone got infos ?

I'm going to generate colors with the 6301 and put them on the first palette register with the 68k, without interrupts, to be able to watch the timings in pixels (one pixels is one cycle in low-res).

Ok, maybe i'm the only coder here to be interrested by this

Post by **simonsunnyboy** » Sun Jan 09, 2005 2:19 pm

Count me in for your results - I'm interested in seeing new techniques on ST hardware in 2005!

tobe · Post by **tobe** » Sun Jan 09, 2005 11:08 pm

I have compiled all i can found in one text file :

Code: Select all

==============================================================================
                               THE IKDB BIBLE

Credits : Stephane Catala - Belzebub / ST Connexion
          STMagazine No 53 - 55

Compiled by Tobe / MJJPROD
Please submit any comment/correction/suggestion to tobe[at]freemind-tobe.com
==============================================================================



                                 MEMORY MAP
==============================================================================
$0000-$001F : Internal registers
$0080-$00FF : Internal RAM (128 bytes)
$F000-$FFFF : Internal ROM (4096 bytes)




                                 INTERRUPTS
==============================================================================
$FFF0 | W | SCI - Serial Communication Interface
$FFF2 | W | TOF - Timer Overflow Flag
$FFF4 | W | OCF - Output Compare Flag
$FFF6 | W | ICF - Input Capture Flag
$FFF8 | W | IRQ1
$FFFA | W | SWI - Software Interrupt
$FFFC | W | NMI - Non Maskable Interrupt
$FFFE | W | RESET




                             INTERNAL REGISTERS
==============================================================================
  * Data Registers
------------------------------------------------------------------------------
$0000    | B | DDR1  | Direction Data Register 1                      | RW
$0001    | B | DDR2  | Direction Data Register 2                      | RW
$0002    | B | DR1   | Data Register 1                                | RW
$0003    | B | DR2   | Data Register 2                                | RW
$0004    | B | DDR3  | Direction Data Register 3                      | RW
$0005    | B | DDR4  | Direction Data Register 4                      | RW
$0006    | B | DR3   | Data Register 3                                | RW
$0007    | B | DR4   | Data Register 4                                | RW
------------------------------------------------------------------------------
  * 16bit Timer
------------------------------------------------------------------------------
$0008    | B | TCSR  | Timer Control/Status Register                  | RW
$0009-A  | W | FRC   | Free Running Counter                           | R0
$000B-C  | W | OCR   | Output Compare Register                        | RW
$000D-E  | W | ICR   | Input Capture Register                         | R0
------------------------------------------------------------------------------
$000F    | B | CSR   | Unused Control/Status Register for DR3 SC1/SC2 |
------------------------------------------------------------------------------
  * Serial Communication Interface
------------------------------------------------------------------------------
$0010    | B | RMCR  | Rate & Mode Control Register                   | RW
$0011    | B | TRCSR | Transmit/Receive Control & Status Register     | RW
$0012    | B | RDR   | Receive Data Register                          | R0
$0013    | B | TDR   | Transmit Data Register                         | W0
------------------------------------------------------------------------------
  * RAM Control
------------------------------------------------------------------------------
$0014    | B | RCR   | RAM Control Register                           | RW
------------------------------------------------------------------------------




1 - DATA REGISTERS
==============================================================================

There's four data registers, each bit of each data register can be set to
read or write by the associated control register :
- a bit 0 in the control register mean an input bit in the data register
- a bit 1 in the control register mean an output bit in the data register
For example, %11100000 in the control register mean :
[0-4] : input bit
[5-7] : output bit
If you read the data register, you will get only the values of bits [0-4].
If you write the data register, you will modify only the values of bits [5-7].

1.1 - Data Register 1
------------------------------------------------------------------------------

This register is mapped to the keyboard's matrix lines. (See keyboard table).
The associated control register (DDR1) is set to all input (%00000000).
(see DR3, DR4, keyboard handling)

1.2 - Data Register 2
------------------------------------------------------------------------------

Bit 0 : Joystick 1 pin 5, output for selecting the 74LS244 (see DR4)
Bit 1 : Left mouse button or joystick 0 Fire button.
Bit 2 : Right mouse button or joystick 1 Fire button.
Bit 3 : Acia TxDATA (6301 receive)
Bit 4 : Acia RxDATA (6301 transmit)

1.3 - Data Register 3
------------------------------------------------------------------------------

Bits 1-7 are mapped to the first seven keyboard's matrix rows. (see keyboard
table).
The associated control register (DDR3) is set to all output (%11111111).
(see DR1, DR4, keyboard handling)

1.4 - Data Register 4
------------------------------------------------------------------------------

Bits 0-7 are mapped to the next height keyboard's matrix rows. (see keyboard
table).
The associated control register (DDR4) is set to all output (%11111111).
This register is also used to read joysticks directions, for this you need to
select the 74LS244 by setting the bit 0 of DR2 to 0, on output, then turn the
DDR4 to all input (%00000000). The four directions of each joystick are then
readable on bits [0-3] and [4-7].
(see DR1, DR3, keyboard handling)




2 - SERIAL COMMUNICATION INTERFACE
==============================================================================

The 6301 communicate with the ACIA trought the bits 3 and 4 of DR2.
The SCI is made of four registers.

2.1 - RDR - Receive Data Register
------------------------------------------------------------------------------

This register contains the byte received from the ACIA.
The bit 3 of TRCSR must be set to 0, to set the bit 3 of DR2 to input.
When a byte is received, the bit 7 of TRCSR is set, and a interrupt
is fired if the bit 4 of TRCSR is set to 1.
The SCI can't receive more byte until you read TRCSR then RDR.
It's mean next bytes are lost.

2.2 - TDR - Transmit Data Registers
------------------------------------------------------------------------------

This register contains the byte to be transimtted to the ACIA.
The bit 1 of TRCSR must be set to 1, to set the bit 4 of DR2 to output.
Once the byte is transmitted, the bit 5 of TRCSR is set to 1, and a
interrupt is fired if the bit 2 of TRCSR is set to 1.

2.3 - TRCSR - Transmit/Receive Control & Status Register
------------------------------------------------------------------------------

This register control the communications.
-Bit 0 (RW) : Wake Up, when set to 1, wait until ten 1 appears on the line,
              then it switch to zero.
-Bit 1 (RW) : Transmit Enable
-Bit 2 (RW) : Transmit Interrupt Enable
-Bit 3 (RW) : Receive Enable
-Bit 4 (RW) : Receive Interrupt Enable
-Bit 5 (RO) : Transmit Data Register Empty, is set to 1 when a byte have been
              sent, and is set to 0 when TRCSR is read then TDR is write.
-Bit 6 (RO) : Overrun or Framing Error, is set to 1 when a byte is received if
              the previous byte was not read, and is set to 0 when TRCSR then
              RDR are read.
-Bit 7 (RO) : Receive Data Register Full, is set to 1 when a byte have been
              received, and is set to zero when TRSCR then RDR are read.

2.4 - RMCR - Rate & Mode Control Register
------------------------------------------------------------------------------

The serial speed MUST be set to 7812.5 on ST.
Bits 0 and 1 control the serial speed:
- %00 : 62500   bits/s
- %01 :  7812.5 bits/s (ACIA compatible)
- %10 :   976.6 bits/s
- %11 :   244.1 bits/s
Bits 2 and 3 select the clock:
- %00 : Bi-Phase, Internal 4Mhz
- %01 : NRZ,      Internal 4Mhz
- %10 : NRZ,      Internal 4Mhz, DR2 bit 2 = clock ouput
- %11 : NRZ,      External,      DR2 bit 2 = clock inpout



3 - TIMER
==============================================================================

The timer can generate interrupts.
It's made of four registers.

3.1 - FRC - 16 bit Free Running Counter
------------------------------------------------------------------------------

This register is read-only.
This counter is incremented at each clock cycle (1mhz). When it reach $FFFF,
the bit 5 of TCSR is set to 1, and the interrupt TOF is fired if the bit 2 of
TCSR is set to 1. Then the value of the counter is set to 0.
After a reset, the value is set to 0.

3.2 - ICR - 16 bit Input Capture Register
------------------------------------------------------------------------------

This register is read-only.
It contains the value of FRC register at the last transition of the bit 0
of DR2. It computes the timing between two external events.
When the value of FRC is catched, the bit 7 of TCSR is set to 1, and an
interrupt ICF is fired if the bit 4 of TCSR is set to 1.

3.3 - OCR - 16 bit Output Compare Register
------------------------------------------------------------------------------

When the value of FRC is equal to the value of OCR, the bit 6 of TCSR is set
to 1 and an interrupt OCF is generated if the bit 3 of TSCR is set to 1.
Also, the bit 0 of TCSR is sent to the bit 1 of DR2, if set to output.
After a reset, the value is set to $FFFF.

3.4 - TCSR - Timer Control & Status Register
------------------------------------------------------------------------------

Bit 0 (RW) : Output Level, this bit is sent to bit 1 of DR2 (if set to ouput)
             when FRC reach the value of OCR.
Bit 1 (RW) : Input Edge, if set to 1, the FRC is catched in the ICR on a up
             transition. If set to 0, on a down transition.
Bit 2 (RW) : Enable Timer Overflow Interrupt, enable the interrupt TOF when
             FRC reach $FFFF.
Bit 3 (RW) : Enable Output Compare Interrupt, enable the interrupt OCF when
             FRC reach the value of OCR.
Bit 4 (RW) : Enable Input Capture Interrupt, enable the interrupt ICF when
             the FRC is catched in the ICR.
Bit 5 (RO) : Timer Overflow Flag, is set to 1 when the FRC reach $FFFF, and
             is set to 0 when the TCSR is read.
Bit 6 (RO) : Output Compare Flag, is set to 1 when the FRC reach the value
             of OCR, and is set to 0 when the TCSR is read and then a value
             is written in the OCR.
Bit 7 (RO) : Input Capture Flag, is set to 1 when the ICR catch the FRC, and
             is set to 0 when TCS then ICR are read.




4 - RAM CONTROL
==============================================================================

This register control the internal RAM:
Bit 6 (RW) : enable internal RAM
Bit 7 (RW) : if set to 1, stay at 1 until vcc-standby is down.




5 - KEYBOARD HANDLING
==============================================================================

5.1 - Reading a key state
------------------------------------------------------------------------------

- Set DDR1 to input (%00000000)
- Set DDR3 & DDR4 to output (%11111111)
- Set all bit of DR3 & DR4 to 1, except for the row wich contains the key you
  want to read.
- Read DR1, look for the line wich contains the key you want to read, 0 mean
  the key is down, 1 mean the key is up.


5.2 - keyboard map
--+----------------------------------+---------------------------------------+
D |               DR3                |                  DR4                  |
R |----------------------------------+---------------------------------------+
1 |  1 |  2 |  3 |  4 |  5 |  6 |  7 |  0 |  1 |  2 |  3 |  4 |  5 |  6 |  7 |
--+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 98 | 97 | 99 |101 |    |
1 |    |    |    |    |  1 |  3 |  5 |  7 |  9 | 11 | 13 | 14 | 72 |100 |102 |
2 |    |    |    |    |  2 |  4 |  6 |  8 | 10 | 12 | 41 | 83 | 71 |103 |105 |
3 |    |    |    |    | 15 | 17 | 19 | 21 | 22 | 24 | 26 | 82 | 75 |104 | 74 |
4 | 29 |    |    |    | 16 | 18 | 20 | 34 | 23 | 25 | 27 | 43 | 80 |106 |108 |
5 |    | 42 |    |    | 30 | 31 | 33 | 35 | 36 | 38 | 39 | 28 | 77 |107 | 78 |
6 |    |    | 56 |    | 96 | 32 | 46 | 48 | 37 | 51 | 52 | 40 |109 |110 |111 |
7 |    |    |    | 54 | 44 | 45 | 47 | 49 | 50 | 57 | 58 | 53 |112 |113 |114 |
--+--------------------------------------------------------------------------+




6301 REGISTERS
==============================================================================

The Hitachi 6301 is made of 7 registers :

- A  :  8 bits register
- B  :  8 bits register
- D  : 16 bits register : A(hi) + B(low)
- X  : 16 bits index register
- S  : 16 bits stack register
- PC : 16 bits program counter register
- SR :  8 bits status register

The SR register:
Bit 0 : Carry 
Bit 1 : oVerflow
Bit 2 : Zero
Bit 3 : Negative
Bit 4 : Interrupt
Bit 5 : Half Carry




6301 ADRESSING MODES
==============================================================================

- Implicit, ex : CLRA,        A=#0
- Immediat, ex : LDAA #$FF,   A=#$FF     ' 8 bits register
                 LDD  #$FFFF, D=#$FFFF   ' 16 bits register
- Direct,   ex : LDAA $0F,    A=($0F)    ' for 8 bits adresses
- Extended, ex : LDAA $1000,  A=($1000)  ' for 16 bits adresses
- Indexed,  ex : LDAA X,$FF,  A=(X+$FF)  ' index + 8 bits immediat unsigned
- Relative, ex : BRA  Label,  PC=PC+#$8  ' signed displacement




6301 INSTRUCTION SET SUMMARY
==============================================================================

 REGISTERS & MEMORY INSTRUCTIONS
+----+---+---+---+---+---+---+------+----------------------------------------+
|Mne |Imp|Rel|Imm|Dir|Ind|Ext|HINZVC| Fonction                               |
+----+---+---+---+---+---+---+------+----------------------------------------+
|CLR |   |   |   |   | 6F| 7F|..0100| M=0                                    |
|CLRA| 4F|   |   |   |   |   |..0100| A=0                                    |
|CLRB| 5F|   |   |   |   |   |..0100| B=0                                    |
|LDAA|   |   | 86| 96| A6| B6|..**0.| A=M                                    |
|LDAB|   |   | C6| D6| E6| F6|..**0.| B=M                                    |
|LDD |   |   | CC| DC| EC| FC|..**0.| D=MM                                   |
|LDS |   |   | 8E| 9E| AE| BE|..**0.| S=MM                                   |
|LDX |   |   | CE| DE| EE| FE|..**0.| X=MM                                   |
|PSHA| 36|   |   |   |   |   |......| (SP)=A,SP-                             |
|PSHB| 37|   |   |   |   |   |......| (SP)=B,SP-                             |
|PSHX| 3C|   |   |   |   |   |......| (SP)=X,SP-                             |
|PULA| 36|   |   |   |   |   |......| SP+,A=(SP)                             |
|PULB| 37|   |   |   |   |   |......| SP+,B=(SP)                             |
|PULX| 38|   |   |   |   |   |......| SP+,X=(SP)                             |
|STAA|   |   |   | 97| A7| B7|..**0.| M=A                                    |
|STAB|   |   |   | D7| E7| F7|..**0.| M=B                                    |
|STD |   |   |   | DD| ED| FD|..**0.| MM=D                                   |
|STS |   |   |   | 9F| AF| BF|..**0.| MM=S                                   |
|STX |   |   |   | DF| EF| FF|..**0.| MM=X                                   |
|TAB | 16|   |   |   |   |   |..**0.| B=A                                    |
|TAP | 06|   |   |   |   |   |******| S=A                                    |
|TBA | 17|   |   |   |   |   |..**0.| A=B                                    |
|TPA | 07|   |   |   |   |   |......| A=S                                    |
+----+---+---+---+---+---+---+------+----------------------------------------+

 ARITHMETIC INSTRUCTIONS                                                    																			 |
+----+---+---+---+---+---+---+------+----------------------------------------+
|Mne |Imp|Rel|Imm|Dir|Ind|Ext|HINZVC| Fonction                               |
+----+---+---+---+---+---+---+------+----------------------------------------+
|ABA | 1B|   |   |   |   |   |*.****| B=B+A                                  |
|ABX | 3A|   |   |   |   |   |......| X=X+B (B unsigned)                     |
|ADCA|   |   | 89| 99| A9| B9|*.****| A=A+M+C                                |
|ADCB|   |   | C9| D9| E9| F9|*.****| B=B+M+C                                |
|ADDA|   |   | 8B| 9B| AB| BB|*.****| A=A+M                                  |
|ADDB|   |   | CB| DB| EB| FB|*.****| B=B+M                                  |
|ADDD|   |   | C3| D3| E3| F3|..****| D=D+MM                                 |
|DAA | 19|   |   |   |   |   |..****| A=BCD(A)                               |
|DEC |   |   |   |   | 6A| 7A|..***.| M=M-1                                  |
|DECA| 4A|   |   |   |   |   |..***.| A=A-1                                  |
|DECB| 5A|   |   |   |   |   |..***.| B=B-1                                  |
|DES | 34|   |   |   |   |   |......| S=S-1                                  |
|DEX | 09|   |   |   |   |   |...*..| X=X-1                                  |
|INC |   |   |   |   | 6C| 7C|..***.| M=M+1                                  |
|INCA| 4C|   |   |   |   |   |..***.| A=A+1                                  |
|INCB| 5C|   |   |   |   |   |..***.| B=B+1                                  |
|INS | 31|   |   |   |   |   |......| S=S+1                                  |
|INX | 08|   |   |   |   |   |...*..| X=X+1                                  |
|MUL | 3D|   |   |   |   |   |.....*| D=A*B                                  |
|NEG |   |   |   |   | 60| 70|..****| M=-M                                   |
|NEGA| 40|   |   |   |   |   |..****| A=-A                                   |
|NEGB| 50|   |   |   |   |   |..****| B=-B                                   |
|SBA | 10|   |   |   |   |   |..****| A=A-B                                  |
|SBCA|   |   | 82| 92| A2| B2|..****| A=A-M-C                                |
|SBCB|   |   | C2| D2| E2| F2|..****| B=B-M-C                                |
|SUBA|   |   | 80| 90| A0| B0|..****| A=A-M                                  |
|SUBB|   |   | C0| D0| E0| F0|..****| B=B-M                                  |
|SUBD|   |   | 83| 93| A3| B3|..****| D=D-MM                                 |
+----+---+---+---+---+---+---+------+----------------------------------------+

 LOGICAL INSTRUCTIONS
+----+---+---+---+---+---+---+------+----------------------------------------+
|Mne |Imp|Rel|Imm|Dir|Ind|Ext|HINZVC| Fonction                               |
+----+---+---+---+---+---+---+------+----------------------------------------+
|ANDA|   |   | 84| 94| A4| B4|..**0.| A=A&M                                  |
|ANDB|   |   | C4| D4| E4| F4|..**0.| B=B&M                                  |
|EORA|   |   | 88| 98| A8| B8|..**0.| A=A^M                                  |
|EORB|   |   | C8| D8| E8| F8|..**0.| B=B^M                                  |
|NOT |   |   |   |   | 63| 73|..**01| M=~M                                   |
|NOTA| 43|   |   |   |   |   |..**01| A=~A                                   |
|NOTB| 53|   |   |   |   |   |..**01| B=~B                                   |
|ORAA|   |   | 8A| 9A| AA| BA|..**0.| A=A|M                                  |
|ORAB|   |   | CA| DA| EA| FA|..**0.| B=B|M                                  |
+----+---+---+---+---+---+---+------+----------------------------------------+

 SHIFT & ROTATE INSTRUCTIONS
+----+---+---+---+---+---+---+------+----------------------------------------+
|Mne |Imp|Rel|Imm|Dir|Ind|Ext|HINZVC| Fonction                               |
+----+---+---+---+---+---+---+------+----------------------------------------+
|ASR |   |   |   |   | 67| 77|..****| M=M>>1                                 |
|ASRA| 47|   |   |   |   |   |..****| A=A>>1                                 |
|ASRB| 57|   |   |   |   |   |..****| B=B>>1                                 |
|LSL |   |   |   |   | 68| 78|..****| M=M<<1                                 |
|LSLA| 48|   |   |   |   |   |..****| A=A<<1                                 |
|LSLB| 58|   |   |   |   |   |..****| B=B<<1                                 |
|LSLD| 05|   |   |   |   |   |..****| D=D<<1                                 |
|LSR |   |   |   |   | 64| 74|..0***| M=M>>1                                 |
|LSRA| 44|   |   |   |   |   |..0***| A=A>>1                                 |
|LSRB| 54|   |   |   |   |   |..0***| B=B>>1                                 |
|LSRD| 04|   |   |   |   |   |..0***| D=D>>1                                 |
|ROL |   |   |   |   | 69| 79|..****| M=M<<1+C (C is previous carry)         |
|ROLA| 49|   |   |   |   |   |..****| A=A<<1+C        //                     |
|ROLB| 59|   |   |   |   |   |..****| B=B<<1+C        //                     |
|ROR |   |   |   |   | 66| 76|..****| M=M>>1+C<<8     //                     |
|RORA| 46|   |   |   |   |   |..****| A=A>>1+C<<8     //                     |
|RORB| 56|   |   |   |   |   |..****| B=B>>1+C<<8     //                     |
+----+---+---+---+---+---+---+------+----------------------------------------+

 TEST & COMPARE INSTRUCTIONS
+----+---+---+---+---+---+---+------+----------------------------------------+
|Mne |Imp|Rel|Imm|Dir|Ind|Ext|HINZVC| Fonction                               |
+----+---+---+---+---+---+---+------+----------------------------------------+
|BITA|   |   | 85| 95| A5| B5|..**0.| A&M                                    |
|BITB|   |   | C5| D5| E5| F5|..**0.| B&M                                    |
|CBA | 11|   |   |   |   |   |..****| B-A                                    |
|CMPA|   |   | 81| 91| A1| B1|..****| A-M                                    |
|CMPB|   |   | C1| D1| E1| F1|..****| B-M                                    |
|CPX |   |   | 8C| 9C| AC| BC|..****| X-MM                                   |
|TST |   |   |   |   | 6D| 7D|..**00| M-0                                    |
|TSTA| 4D|   |   |   |   |   |..**00| A-0                                    |
|TSTB| 5D|   |   |   |   |   |..**00| B-0                                    |
+----+---+---+---+---+---+---+------+----------------------------------------+

 STATUS REGISTER INSTRUCTIONS
+----+---+---+---+---+---+---+------+----------------------------------------+
|Mne |Imp|Rel|Imm|Dir|Ind|Ext|HINZVC| Fonction                               |
+----+---+---+---+---+---+---+------+----------------------------------------+
|CLC | 0C|   |   |   |   |   |.....0| C=0                                    |
|CLI | 0E|   |   |   |   |   |.0....| I=0                                    |
|CLV | 0A|   |   |   |   |   |....0.| V=0                                    |
|SEC | 0D|   |   |   |   |   |.....1| C=1                                    |
|SEI | 0F|   |   |   |   |   |.1....| I=1                                    |
|SEV | 0B|   |   |   |   |   |....1.| V=1                                    |
+----+---+---+---+---+---+---+------+----------------------------------------+

 BRANCHING INSTRUCTIONS
+----+---+---+---+---+---+---+------+----------------------------------------+
|Mne |Imp|Rel|Imm|Dir|Ind|Ext|HINZVC| Fonction                               |
+----+---+---+---+---+---+---+------+----------------------------------------+
|BCC |   | 24|   |   |   |   |......| if C=0 then PC=PC+M                    |
|BCS |   | 25|   |   |   |   |......| if C=1 then PC=PC+M                    |
|BEQ |   | 27|   |   |   |   |......| if Z=1 then PC=PC+M                    |
|BGE |   | 2C|   |   |   |   |......| if N^V=0 then PC=PC+M                  |
|BGT |   | 2E|   |   |   |   |......| if Z|(N^V) then PC=PC+M                |
|BHI |   | 22|   |   |   |   |......| if C|Z=0 then PC=PC+M                  |
|BLE |   | 2F|   |   |   |   |......| if Z|(N^V)=1 then PC=PC+M              |
|BLS |   | 23|   |   |   |   |......| if C|Z=1 then PC=PC+M                  |
|BLT |   | 2D|   |   |   |   |......| if N^V=1 then PC=PC+M                  |
|BMI |   | 2B|   |   |   |   |......| if N=1 then PC=PC+M                    |
|BNE |   | 26|   |   |   |   |......| if Z=0 then PC=PC+M                    |
|BPL |   | 2A|   |   |   |   |......| if N=0 then PC=PC+M                    |
|BVC |   | 28|   |   |   |   |......| if V=0 then PC=PC+M                    |
|BVS |   | 29|   |   |   |   |......| if V=1 then PC=PC+M                    |
|BRA |   | 20|   |   |   |   |......| PC=PC+M                                |
|BRN |   | 21|   |   |   |   |......| PC=PC+0                                |
|BSR |   | 8D|   |   |   |   |......| (SP)=PC,SP-,PC=PC+M                    |
|JMP |   |   |   |   | 6E| 7E|......| PC=MM                                  |
|JSR |   |   |   | 9D| AD| BD|......| (SP)=PC,SP-,PC=PC+M                    |
+----+---+---+---+---+---+---+------+----------------------------------------+

 OTHER INSTRUCTIONS
+----+---+---+---+---+---+---+------+----------------------------------------+
|Mne |Imp|Rel|Imm|Dir|Ind|Ext|HINZVC| Fonction                               |
+----+---+---+---+---+---+---+------+----------------------------------------+
|NOP | 01|   |   |   |   |   |......|                                        |
|RTI | 3B|   |   |   |   |   |******| Ret Interrupt                          |
|RTS | 39|   |   |   |   |   |......| Ret                                    |
|SWI | 3F|   |   |   |   |   |.1....| PC=SWI                                 |
|WAI | 3E|   |   |   |   |   |......| PC=PC-1                                |
+----+---+---+---+---+---+---+------+----------------------------------------+

 ADDITIONAL INSTRUCTIONS (6301 only)
+---+------+---+-------------------------------------------------------------+
|AND| #x,M | 71| M=M&x                                                       |
|OR | #x,M | 72| M=M|x                                                       |
|EOR| #x,M | 75| M=M^x                                                       |
|BIT| #x,M | 7B| M&x                                                         |
+---+------+---+-------------------------------------------------------------+

I wrote the reusable code uploader, it seems to work, now i must write a small test and pack all this in a nice zip

tobe · Post by **tobe** » Mon Jan 10, 2005 5:55 pm

That's done !

You can download the ZIP here :
http://atari.freemind-tobe.com/HD6301.ZIP

Code: Select all

This package contains :

- README.TXT
- HD6301.TXT   : the Hitachi 6301 docs
- IKBD_UPL.S   : a reusable 6301 code uploader
- IKBD_TST.S   : a test for IKBD_UPL.S
- IKBD_TST.PRG : the compiled version

TOBE/MJJPROD

The test PRG is designed for ST(E), note that when you launch it you can't exit and you must RESET.

Of course, it will not run under emulators

Post by **ggn** » Tue Jan 11, 2005 7:10 am

Will test it this evening

Atari-Forum

Keyboard controller

Keyboard controller

Re: Keyboard controller

Re: Keyboard controller