Identify This Board?

[czietz]

I can send you the PCB if you want to do further analysis on it?

Yes, thank you! Now that I've gotten so far, I'd really like to know if my assumptions about the flip-flip and NAND gate connections are right.

I'll send you my address via PM.

[ijor]

Pseudo-code of the interrupt handler in the 8048:

Great work Christian. Would you mind providing the disassembler output. I think it is more useful than seudocode.

I can't be sure because I cannot see all the PCB traces. But P2.5 seems to gate the "read data" line, i.e., the line where data is being transmitted from the floppy to the computer/controller, by using the NAND gate. If I understand it correctly, the "step_one_track_higher" and "step_one_track_lower" routines block "read data" and (re-)start a countdown. If this countdown expires in the main loop (after ca. 20 ms after the last step command, assuming 6 MHz), "read data" is unblocked again. This effectively introduces a head-settle delay.

It is likely that READ is blocked and delayed. I would expect gating TRACK0 as well, otherwise it could create a potential incompatibility. But all those delays also introduce some level of incompatibility, probably even more severe, and they can't help it anyway. In theory MOTOR should also be gated, but in practice it is not needed because of the way the FDC works.

Interesting what was all the story about this. Did Atari find some cheaper drives that required a slower step rate? Wonder how much they saved.

Btw, this still doesn't explain why some SF354 boards don't work with double sided drives.

[czietz]

Great work Christian. Would you mind providing the disassembler output. I think it is more useful than seudocode.

See attachment. It's an export from my Ghidra project, i.e., it would need some post processing before you can assemble it again.

disassembly.txt

It is likely that READ is blocked and delayed. I would expect gating TRACK0 as well

This could even be on the board. I couldn't follow all traces. Now that Zippy is going to send me the board, I'll continuity test that theory, too.

Interesting what was all the story about this. Did Atari find some cheaper drives that required a slower step rate? Wonder how much they saved.

It's all speculation, but I can think of several ways how this could have made sense on the business side:
a. As you already wrote, maybe Atari got the drives cheap. Perhaps precisely because they're so special. Thus, developing and manufacturing the adapter board paid itself off. [1]
b. Maybe, floppy drives were so scarce at some point in time that the only other option would have been to stop production. So, they begrudgingly accepted the extra cost.
c. Or they had already ordered and stocked a million of these drives before finding out about the step rate.

Btw, this still doesn't explain why some SF354 boards don't work with double sided drives.

Maybe side select was simply not routed through?

[1] As for getting stuff cheap: I have some SIMMs from an STE -- presumably original, because the warranty seal was still on. There, Atari used 3 x 3(!) bit DRAMs to get to 8 bit. 3 bit DRAMs, you might ask. These are 4 bit DRAMs where at least one bit is defective. Solder bridges on the SIMM PCB allow a selection which data line not to use. Even with the extra effort of (probably manually) configuring each SIMM, this must have been cheaper. That way, Atari could buy the scrapped parts from a DRAM manufacturer.

[Zippy]

I'll post you the board this afternoon, so should be with you next week.

Does Ghidra specifically support the MCS48 series of mcu's or did you select some other Intel 8 bit cpu to get the disassembly?

I tried with IDA Pro but my version doesn't support MSC48 and trying with other 8 bit Intel chips like 8051 doesn't give a good disassembly like yours.

[1] As for getting stuff cheap: I have some SIMMs from an STE -- presumably original, because the warranty seal was still on. There, Atari used 3 x 3(!) bit DRAMs to get to 8 bit. 3 bit DRAMs, you might ask. These are 4 bit DRAMs where at least one bit is defective. Solder bridges on the SIMM PCB allow a selection which data line not to use. Even with the extra effort of (probably manually) configuring each SIMM, this must have been cheaper. That way, Atari could buy the scrapped parts from a DRAM manufacturer.

Chuck Peddle (the guy who made the 6502) was doing similar stuff at the die level with DRAM around the same time , some interesting stuff here at 3:29:28 into the video:

https://www.youtube.com/watch?v=enHF9lMseP8

[ijor]

See attachment. It's an export from my Ghidra project, i.e., it would need some post processing before you can assemble it again.

Thanks.

This could even be on the board. I couldn't follow all traces. Now that Zippy is going to send me the board, I'll continuity test that theory, too.

Thinking more about this, INDEX should be gated as well, otherwise the computer might start formatting a track too early. Possibly WGATE could also be gated. This seems even more important than gating READ.

Does Ghidra specifically support the MCS48 series of mcu's or did you select some other Intel 8 bit cpu to get the disassembly?
I tried with IDA Pro but my version doesn't support MSC48 and trying with other 8 bit Intel chips like 8051 doesn't give a good disassembly like yours.

The 8051 is Intel next generation MCU, it's not binary compatible with the 8048.

There should be free MCS-48 tools online, including assembler, disassembler, and even simulators. Google and you should fine at least a couple.

[czietz]

Does Ghidra specifically support the MCS48 series of mcu's or did you select some other Intel 8 bit cpu to get the disassembly?

8048 is one of the supported architectures in Ghidra.

[ijor]

- P1.2 not certain, could be connected to the index line of the floppy drive.
...
They also do something with P2.5.

If P2.5 is indeed the index pulse (probably it is) and if the index signal is gated, then it seems that the code is trying to avoid generating a partial late index pulse. This could be important because otherwise a track might be formatted not correctly aligned with the actual index hole position.

EDIT: And, if the direction has changed compared to the last step, they will add an additional delay before switching the direction pin and doing the step.

This is quite interesting. It is not just a small additional delay. I wonder why they do that. The FDC doesn't perform any extra delay when switching step direction. I wonder if this actually was an additional requirement of these drives.

P1.1 and T1 are both connected to track 0 sensor of the floppy drive. (This means that the SW can also use the event counter of the 8048 to detect that track 0 has been reached.)

This is also quite strange. The check for track0 by detecting an edge seems unnecessarily overcomplicated.

[Zippy]

Got the board from MiggyMog today, thanks. It's the same as the board in the 1st picture of the thread except that the 4 logic chips are surface mounted (soldered by hand and not even straight in 1 case!). The code on the 8048 is identical to that used in the other board design, so probably all these boards use the same code.

I can send you this board as well if you'd like it for testing czietz? Might be better than the other one I butchered desoldering the MCU as this one was socketed.

And the crystal is marked 6.0M so I guess that confirms the 6Mhz theory.

[ijor]

At this point I am more curious about the similar board present on some external SF354 drives. Guess it would be harder to find. Anybody here have one of those?

Btw, the more I think about this, the more potential compatibility issues I find. The worst case would be in a setup with two drives where both drives might be selected (one by the computer, the other by the internal board) and interfere with each other. This might actually be the main reason why some signals are gated.

[czietz]

I can send you this board as well if you'd like it for testing czietz? Might be better than the other one I butchered desoldering the MCU as this one was socketed.

Thank you. But let me first see (as soon as I receive and trace the first board) if there will be any remaining open questions that require testing on a live board.

[czietz]

Meanwhile, I received the board from Zippy. (Thank you!) I meticulously continuity tested all(?) connections. Hopefully, I'll have time to draw a schematic during the weekend.

In any case, ijor was right about the index signal being gated. Index and read data are gated by P2.5 of the 8048, introducing a head settle delay.

Even more interesting: Read data and write gate are also gated by the side select signal, i.e., they're only allowed to pass through for side 0. This explains why double-sided drives do not work with this add-on board. I can again only speculate, but maybe the drive this is meant for -- being single-sided -- does not evaluate the side select signal, at all. Then, without gating, any attempted access to side 1 would have in fact accessed side 0.

[ijor]

In any case, ijor was right about the index signal being gated. Index and read data are gated by P2.5 of the 8048, introducing a head settle delay.

And Index is also the unknown, P1.2, input?
Where the P2.0 output is connected?

Even more interesting: Read data and write gate are also gated by the side select signal, i.e., they're only allowed to pass through for side 0 ...

Interesting indeed and this explains why double sided drives don't work.

Thanks,

[czietz]

And Index is also the unknown, P1.2, input?
Where the P2.0 output is connected?

The Index signal is in fact also connected to the P1.2 input. P2.0 is combined with drive select 0 from the computer to produce the the drive select signal for the drive -- so that computer and 8048 can both select the drive. More details in the upcoming schematic.

[sety]

Btw, the more I think about this, the more potential compatibility issues I find. The worst case would be in a setup with two drives where both drives might be selected (one by the computer, the other by the internal board) and interfere with each other. This might actually be the main reason why some signals are gated.

If it's of any use, I just remembered that the computer I found that thing in had (at one time) two internal floppy drives fitted. The previous owner had cut away enough of top case (though the diagonal fins) to run a ribbon cable and drilled holes to screw a floppy drive on top of the case above the existing drive. It's also been sliced up to allow a PC floppy drive to be mounted in the normal bay.

That whole computer was so far gone that I ended up parting it (which I hate doing - One more ST written off the planet) but it was really bad.

[ijor]

Btw, the more I think about this, the more potential compatibility issues I find. The worst case would be in a setup with two drives where both drives might be selected (one by the computer, the other by the internal board) and interfere with each other. This might actually be the main reason why some signals are gated.

If it's of any use, I just remembered that the computer I found that thing in had (at one time) two internal floppy drives fitted.

It should normally work ok with two drives because of the way that TOS accesses floppies. The problem can arise if the computers steps one drive and then immediately tries to access the other. In such a cases both drives might be selected simultaneous. One by the computer and the other by the logic on this board that didn't finish the step yet.

TOS doesn't step one drive and then immediately tries to access the other. But software that bypasses TOS to access the floppy might.

[sety]

I may have gotten it completely wrong. Sorry, I bought these machines about 5 years ago and my memory is a bit hazy.

I bought 2 STs as a pair from a music studio. One was the butchered with PC drive mod and in terrible condition but working. The other was immaculate but dead.

The seller told me he didn't have time to get it repaired so he went and bought a new one, and the broken one sat in a box for 30 years. Now that I think about it, I think that weird card was in the latter.

The good news is that I may still have the drive that went with that card. It would be the only long button floppy I own. If I find it I'll let you know.

[MiggyMog]

I still have the drive which was with the board I sent to zippy.

[czietz]

More details in the upcoming schematic.

Schematic is attached. I have cross-checked it against my notes and -- previously -- I had checked my notes against the actual board. So, it should be accurate -- hopefully.

[ijor]

I still have the drive which was with the board I sent to zippy.

Well, for starters it might be nice to have pictures of the drive. May be one that shows the brand and the model if you can.

May be to perform some tests without the board, connected directly like a "normal" drive, could be very interesting. But there is a small risk that it could be dangerous. Probably should be ok, in the worst case it just won't work, but it's difficult to be 100% sure and not sure it is worth the risk.

Schematic is attached.

Thanks. Good work! I was missing one NAND gate, and assumed they might have just wired two open collectors outputs. Doing that in the most sensitive signal (READ), not sure it is a very good idea though.

[czietz]

Well, for starters it might be nice to have pictures of the drive. May be one that shows the brand and the model if you can.

Over in the German forum (https://forum.atari-home.de/index.php/t ... #msg251452) someone with a similar board found it attached to a Chinon F353AT drive. I couldn't find any info on that drive, though.

[czietz]

PS: I'm going to hold on to the board Zippy sent me for a little while, in case there are any questions/doubts about the schematic. Is there someone else who wants to do something with the board then? I could send it on. (Zippy desoldered some ICs, as you know, but they are present, including the 8048.)

[GrahamN]

Thanks very much - I don't get to the board very often, so please accept my apologies for not realising I had a response sooner.

Does anyone want it?

I'm happy to send it for the cost of postage (100g large letter) if it's any good to anyone.

[MiggyMog]

connectsfatari.jpg

This is where it connects on dodgy old single sided drive

And circuit rear , a bit fuzzy after resizing to board limits

20200830_130544.jpg

[czietz]

PS: Using my newly bought "toy", I confirmed (by measurement) that the "6000 NMZ" marked Fujitsu part is, as already assumed, a 6 MHz resonator. Due to the fact that it has three pins and due to the frequency deviation from nominal 6 MHz, I suppose it's a ceramic resonator and not a quartz crystal.

The 8048 running at roughly 6 MHz means that the timings I calculated in this thread (e.g. in https://www.atari-forum.com/viewtopic.p ... 99#p404199) are correct.

6000nmz.png