Yes, thank you! Now that I've gotten so far, I'd really like to know if my assumptions about the flip-flip and NAND gate connections are right.
I'll send you my address via PM.
Great work Christian. Would you mind providing the disassembler output. I think it is more useful than seudocode.
It is likely that READ is blocked and delayed. I would expect gating TRACK0 as well, otherwise it could create a potential incompatibility. But all those delays also introduce some level of incompatibility, probably even more severe, and they can't help it anyway. In theory MOTOR should also be gated, but in practice it is not needed because of the way the FDC works.I can't be sure because I cannot see all the PCB traces. But P2.5 seems to gate the "read data" line, i.e., the line where data is being transmitted from the floppy to the computer/controller, by using the NAND gate. If I understand it correctly, the "step_one_track_higher" and "step_one_track_lower" routines block "read data" and (re-)start a countdown. If this countdown expires in the main loop (after ca. 20 ms after the last step command, assuming 6 MHz), "read data" is unblocked again. This effectively introduces a head-settle delay.
See attachment. It's an export from my Ghidra project, i.e., it would need some post processing before you can assemble it again.
This could even be on the board. I couldn't follow all traces. Now that Zippy is going to send me the board, I'll continuity test that theory, too.
It's all speculation, but I can think of several ways how this could have made sense on the business side:
Maybe side select was simply not routed through?
Chuck Peddle (the guy who made the 6502) was doing similar stuff at the die level with DRAM around the same time , some interesting stuff here at 3:29:28 into the video:czietz wrote: ↑Mon Aug 10, 2020 5:43 am  As for getting stuff cheap: I have some SIMMs from an STE -- presumably original, because the warranty seal was still on. There, Atari used 3 x 3(!) bit DRAMs to get to 8 bit. 3 bit DRAMs, you might ask. These are 4 bit DRAMs where at least one bit is defective. Solder bridges on the SIMM PCB allow a selection which data line not to use. Even with the extra effort of (probably manually) configuring each SIMM, this must have been cheaper. That way, Atari could buy the scrapped parts from a DRAM manufacturer.
Thinking more about this, INDEX should be gated as well, otherwise the computer might start formatting a track too early. Possibly WGATE could also be gated. This seems even more important than gating READ.
The 8051 is Intel next generation MCU, it's not binary compatible with the 8048.Zippy wrote: ↑Mon Aug 10, 2020 9:12 am Does Ghidra specifically support the MCS48 series of mcu's or did you select some other Intel 8 bit cpu to get the disassembly?
I tried with IDA Pro but my version doesn't support MSC48 and trying with other 8 bit Intel chips like 8051 doesn't give a good disassembly like yours.
If P2.5 is indeed the index pulse (probably it is) and if the index signal is gated, then it seems that the code is trying to avoid generating a partial late index pulse. This could be important because otherwise a track might be formatted not correctly aligned with the actual index hole position.
This is quite interesting. It is not just a small additional delay. I wonder why they do that. The FDC doesn't perform any extra delay when switching step direction. I wonder if this actually was an additional requirement of these drives.EDIT: And, if the direction has changed compared to the last step, they will add an additional delay before switching the direction pin and doing the step.
This is also quite strange. The check for track0 by detecting an edge seems unnecessarily overcomplicated.P1.1 and T1 are both connected to track 0 sensor of the floppy drive. (This means that the SW can also use the event counter of the 8048 to detect that track 0 has been reached.)
Thank you. But let me first see (as soon as I receive and trace the first board) if there will be any remaining open questions that require testing on a live board.
And Index is also the unknown, P1.2, input?
Interesting indeed and this explains why double sided drives don't work.Even more interesting: Read data and write gate are also gated by the side select signal, i.e., they're only allowed to pass through for side 0 ...
The Index signal is in fact also connected to the P1.2 input. P2.0 is combined with drive select 0 from the computer to produce the the drive select signal for the drive -- so that computer and 8048 can both select the drive. More details in the upcoming schematic.
If it's of any use, I just remembered that the computer I found that thing in had (at one time) two internal floppy drives fitted. The previous owner had cut away enough of top case (though the diagonal fins) to run a ribbon cable and drilled holes to screw a floppy drive on top of the case above the existing drive. It's also been sliced up to allow a PC floppy drive to be mounted in the normal bay.ijor wrote: ↑Thu Aug 13, 2020 3:15 pm Btw, the more I think about this, the more potential compatibility issues I find. The worst case would be in a setup with two drives where both drives might be selected (one by the computer, the other by the internal board) and interfere with each other. This might actually be the main reason why some signals are gated.
It should normally work ok with two drives because of the way that TOS accesses floppies. The problem can arise if the computers steps one drive and then immediately tries to access the other. In such a cases both drives might be selected simultaneous. One by the computer and the other by the logic on this board that didn't finish the step yet.sety wrote: ↑Fri Aug 21, 2020 9:31 amIf it's of any use, I just remembered that the computer I found that thing in had (at one time) two internal floppy drives fitted.ijor wrote: ↑Thu Aug 13, 2020 3:15 pm Btw, the more I think about this, the more potential compatibility issues I find. The worst case would be in a setup with two drives where both drives might be selected (one by the computer, the other by the internal board) and interfere with each other. This might actually be the main reason why some signals are gated.
Schematic is attached. I have cross-checked it against my notes and -- previously -- I had checked my notes against the actual board. So, it should be accurate -- hopefully.
Well, for starters it might be nice to have pictures of the drive. May be one that shows the brand and the model if you can.
Thanks. Good work! I was missing one NAND gate, and assumed they might have just wired two open collectors outputs. Doing that in the most sensitive signal (READ), not sure it is a very good idea though.
Over in the German forum (https://forum.atari-home.de/index.php/t ... #msg251452) someone with a similar board found it attached to a Chinon F353AT drive. I couldn't find any info on that drive, though.