MFP internals

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slingshot
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MFP internals

Post by slingshot »

Is there any information available about the internal timings of the MFP? Most importantly interrupt delays?
Just did an experiment with some bottom border removing demo + FPGA. To work properly, some delay must happen between DE asserted and the Timer B interrupt. But what would be the exact value? I assume that must be some timer clock cycles (even if the event counting mode doesn't really use the timer xtal).
neanderthal
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Re: MFP internals

Post by neanderthal »

Semi old one this one..but interesting question.Never thought about it..I would quess it would depend on CLK4 or something? Ie when TBI is latched into internal circuitry of MFP..was a good while since read the docus about MFP.
slingshot
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Re: MFP internals

Post by slingshot »

I've experimented a lot in Verilog with this, seems the interrupt itself is not delayed too much, but the external timer input to the timer output is. Demos started to work correctly when I applied a 8 MFP clock (4Mhz) delay to the input. I don't say it's the correct behavior, but works so far. From my POV the MFP datasheet is ambiguous in this question (as datasheets usually behave).
TomH
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Re: MFP internals

Post by TomH »

Sorry, late revival: I'm unclear what your 4Mhz number is meant to describe, but I think the main hint in the MFP data sheet is "To count [event] transitions reliably, the input must remain in each state (1/O) for a length of time equal to four periods of the timer clock ; thus signals of a frequency up to one fourth of the timer clock can be counted" which implies a delay for event counting of something greater than 3 and less than 4 cycles.

In an ST the MFP is clocked at 2,457,600Mhz.
Gunstick
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Re: MFP internals

Post by Gunstick »

As the MFP has a different quartz than the rest of the ST, I guess that there may be random delays. Most emulators set a fixed ratio between the 2 quartz but in fact they are diverging and can even drift with temperature. But the overscan points are not that precise, you can be 4-8 clock cycles off.

Maybe I could write a test program which displays color changes for synced code, timer interrupt and hbl interrupt positions?
slingshot
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Re: MFP internals

Post by slingshot »

Gunstick wrote:As the MFP has a different quartz than the rest of the ST, I guess that there may be random delays. Most emulators set a fixed ratio between the 2 quartz but in fact they are diverging and can even drift with temperature. But the overscan points are not that precise, you can be 4-8 clock cycles off.

Maybe I could write a test program which displays color changes for synced code, timer interrupt and hbl interrupt positions?
I would be very thankful for that. Currently I calibrated the DE-to timer interrupt delay to make bottom border opening effects happy (and the rest of the MFP using your DSOTS demo - since it has a very long running timer and has to fire its irq at a precise location), but having a test program for this would be the best. This kind of test would show the jitter introduced by the CPU-MFP async clocks.
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