Open Source 68K Accelerator Project(s)
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- Atari freak
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Open Source 68K Accelerator Project(s)
Hi Folks,
Apologies if this is not relevant but it was suggested to me that people on this forum may be interested in my 68K accelerator project and the video series I have about it. Although I am not focusing on the Atari ST i do have a few STs kicking around and I will be trying to bring the board up for the STFM soon. My channel is at
https://www.youtube.com/channel/UCu4uiU ... rribleFire
And all the code and sources are being published on GitHUB, Its all prototype at the moment but it is working on the A500 already. I have plans to make more complex boards in future as things progress. All the code is available at...
https://github.com/terriblefire/tf520
Currently I have a 68020 only board. I have plans to build a 68030 + FPU board in the near future. I will say though that I make no promises about anything except that I will keep everything open source and GPLd.
Regards
Stephen
Apologies if this is not relevant but it was suggested to me that people on this forum may be interested in my 68K accelerator project and the video series I have about it. Although I am not focusing on the Atari ST i do have a few STs kicking around and I will be trying to bring the board up for the STFM soon. My channel is at
https://www.youtube.com/channel/UCu4uiU ... rribleFire
And all the code and sources are being published on GitHUB, Its all prototype at the moment but it is working on the A500 already. I have plans to make more complex boards in future as things progress. All the code is available at...
https://github.com/terriblefire/tf520
Currently I have a 68020 only board. I have plans to build a 68030 + FPU board in the near future. I will say though that I make no promises about anything except that I will keep everything open source and GPLd.
Regards
Stephen
Re: Open Source 68K Accelerator Project(s)
Interesting stuff! Will check out your channel over the weekend.
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- Atari freak
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Re: Open Source 68K Accelerator Project(s)
I've heard that there are adaptor boards to adapt the STe PLCC CPU socket out to the big DIL sockets... Are these readily available?
Re: Open Source 68K Accelerator Project(s)
I'm not aware of anyone whos done that adaption no. Mostly dip to plcc are for the stfm like this one http://www.exxoshost.co.uk/atari/last/V ... /index.htmterriblefire wrote:I've heard that there are adaptor boards to adapt the STe PLCC CPU socket out to the big DIL sockets... Are these readily available?
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- Atari freak
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Re: Open Source 68K Accelerator Project(s)
Thanks. No worries. I've got a reasonable knowledge of the ST machines from my FPGA clone days (I had an Atari ST FPGA clone build in the Digilent Atlys which was abandoned and the best bits incorporated into the MiST project) and a few contributions to the EmuTOS project which have been re-written now.exxos wrote:I'm not aware of anyone whos done that adaption no. Mostly dip to plcc are for the stfm like this one http://www.exxoshost.co.uk/atari/last/V ... /index.htmterriblefire wrote:I've heard that there are adaptor boards to adapt the STe PLCC CPU socket out to the big DIL sockets... Are these readily available?
The idea with my board is to keep it open and cheap. I dont have plans to sell them myself simply ensure there is always the means to do it cheaply.
Re: Open Source 68K Accelerator Project(s)
Sounds cool
so have you done a FPGA 68k then ? I think while the 68k maxes out at 32mhz, if a FPGA could bash out higher speeds then that would make a really interesting project.

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- Atari freak
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Re: Open Source 68K Accelerator Project(s)
I've patched up some to work correctly. I then moved on to do an Archimedes core and decided I wanted to get dirty building hardware again.exxos wrote:Sounds coolso have you done a FPGA 68k then ? I think while the 68k maxes out at 32mhz, if a FPGA could bash out higher speeds then that would make a really interesting project.
I've just hacksawed the 68000 off an old Atari STFM i found in my garage and plugged in my board running off the internal 8Mhz clock. Its sitting looping over some address range. Does anyone know if the original ST ROM (1.01 / 1.02) has compatibility issues with the 68020? If i jam the bus error pins on i see bombs so i know something can compute.
Cheers
Stephen
Re: Open Source 68K Accelerator Project(s)
I'm not 100% sure, but I think you need TOS206 to use the 020 CPU.terriblefire wrote: I've just hacksawed the 68000 off an old Atari STFM i found in my garage and plugged in my board running off the internal 8Mhz clock. Its sitting looping over some address range. Does anyone know if the original ST ROM (1.01 / 1.02) has compatibility issues with the 68020? If i jam the bus error pins on i see bombs so i know something can compute.
Cheers
Stephen
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- Atari freak
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Re: Open Source 68K Accelerator Project(s)
Thanks.. Thats going to be a pain on this ancient machine. Perhaps EmuTOS is my friend.exxos wrote:I'm not 100% sure, but I think you need TOS206 to use the 020 CPU.terriblefire wrote: I've just hacksawed the 68000 off an old Atari STFM i found in my garage and plugged in my board running off the internal 8Mhz clock. Its sitting looping over some address range. Does anyone know if the original ST ROM (1.01 / 1.02) has compatibility issues with the 68020? If i jam the bus error pins on i see bombs so i know something can compute.
Cheers
Stephen
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- Atari Super Hero
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Re: Open Source 68K Accelerator Project(s)
Yes you need a TOS 2.06 for the 68020 to work on a STE (see our 68020 card in a STE there : http://www.atari-forum.com/viewtopic.ph ... 12#p300844).
We have both 68020 card working on a STE with TOS 2.06 and a MegaSTE with TOS 2.06.
There are "patched" version of previous TOS but yea, TOS 2.06 or EmuTOS at this point is the safest bet.
Regards, Rodolphe
We have both 68020 card working on a STE with TOS 2.06 and a MegaSTE with TOS 2.06.
There are "patched" version of previous TOS but yea, TOS 2.06 or EmuTOS at this point is the safest bet.
Regards, Rodolphe
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Re: Open Source 68K Accelerator Project(s)
exxos is right, TOS 1.x does not support the 68010+ stackframes. 192Kb EmuTOS is a direct replacement for TOS 1.x, although it's not much work to add an address decoder for the TOS 2 address range. I would say that is mandatory for any accelerator nowterriblefire wrote:Thanks.. Thats going to be a pain on this ancient machine. Perhaps EmuTOS is my friend.exxos wrote:I'm not 100% sure, but I think you need TOS206 to use the 020 CPU.

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Re: Open Source 68K Accelerator Project(s)
Indeed,terriblefire wrote:Perhaps EmuTOS is my friend.
- EmuTOS supports any CPU
- it automatically detects optional hardware
- it can be compiled to run at any address
- it is easily modifiable and compilable, traces can easily be added
So yes, EmuTOS is your friend to debug hardware issues, and more

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Re: Open Source 68K Accelerator Project(s)
terriblefire great project. I keep finger crossed.
http://www.atari.org.pl/forum/viewtopic ... 40#p224340
TOS 1.06 and 1.62 does support 68010joska wrote:exxos is right, TOS 1.x does not support the 68010+ stackframes.
http://www.atari.org.pl/forum/viewtopic ... 40#p224340
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Re: Open Source 68K Accelerator Project(s)
Maybe, but not on an STFM 

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- Obsessive compulsive Atari behavior
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Re: Open Source 68K Accelerator Project(s)
Will those work on 1040STF too?
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- Atari freak
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Re: Open Source 68K Accelerator Project(s)
I managed to get hold of a T_Board. Just need to set it up to run without the internal romsmatej wrote:Will those work on 1040STF too?
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- Atari freak
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- Atari freak
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Re: Open Source 68K Accelerator Project(s)
My feeling is that the write to disable interrupts from the MFP is failing.terriblefire wrote:Latest update.. not working with TOS 2.06 :/
https://www.youtube.com/watch?v=xrdqksZ ... ture=share
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Re: Open Source 68K Accelerator Project(s)
Afair, the MFP under normal operation shouldn't cause a level 6 auto-vector interrupt but it should provide its own vector number according to the interrupt source. Maybe this interrupt acknowledge cycle (during which the MFP transmits the vector to the CPU) isn't working properly? (Also, unfortunately the decoded addresses in the video are very hard to see, so I can't tell to which part in the boot process you actually get before it hangs.)
Re: Open Source 68K Accelerator Project(s)
In such an interrupt acknowledge cycle the MFP puts the vector number on the data bus and asserts DTACK. On the 68020 your CPLD has to assert DSACK0 and/or DSACK1 instead of AVEC in this case. From looking at your Verilog source code I don't see this happening.
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Re: Open Source 68K Accelerator Project(s)
On a ST, only the ACIA should trigger AVEC.
Here is our VHDL code from our working 68020 card :
AVEC <= not FC2 or not FC1 or not FC0 or not A19 or not A18 or not A17 or not A16 or VPA;
In the case of the MFP, it triggers a level 6 interrupt and wait for IACK from the GLUE (which is asserted when the GLUE detect an interrupt ack cycle from the CPU), it then put the interrupt vector on D0-D7 and assert DTACK. This ends up on the 68020 D24-D31 so you should assert DSACK1 in that case (16 bit transfer and the CPU know to get the 8 high bits it needs for the vector).
Regards, Rodolphe
Here is our VHDL code from our working 68020 card :
AVEC <= not FC2 or not FC1 or not FC0 or not A19 or not A18 or not A17 or not A16 or VPA;
In the case of the MFP, it triggers a level 6 interrupt and wait for IACK from the GLUE (which is asserted when the GLUE detect an interrupt ack cycle from the CPU), it then put the interrupt vector on D0-D7 and assert DTACK. This ends up on the 68020 D24-D31 so you should assert DSACK1 in that case (16 bit transfer and the CPU know to get the 8 high bits it needs for the vector).
Regards, Rodolphe
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Re: Open Source 68K Accelerator Project(s)
Can you point me to where this is mentioned in the 68020 manual. The bits i read said AVEC needed to get asserted but i may have missed this bit. Sorry about the video quality. I need to work more on the open broadcaster settings.czietz wrote:In such an interrupt acknowledge cycle the MFP puts the vector number on the data bus and asserts DTACK. On the 68020 your CPLD has to assert DSACK0 and/or DSACK1 instead of AVEC in this case. From looking at your Verilog source code I don't see this happening.
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Re: Open Source 68K Accelerator Project(s)
OK i'm pretty sure i do this.rpineau wrote:On a ST, only the ACIA should trigger AVEC.
Here is our VHDL code from our working 68020 card :
AVEC <= not FC2 or not FC1 or not FC0 or not A19 or not A18 or not A17 or not A16 or VPA;
wire CPUSPACE = &FC;
(which is the logical reduction of FC)
wire IACK = CPUSPACE & ({A[19:16]} == {4'b1111});
Then
assign AVEC = IACK & ~VPA;
Note that my CPLD doesnt have crazy inverting logic like PALs.
I may be missing this bit then. How does this cycle get distinguished from other bus cycles if it happens after the IACK part of the cycle?rpineau wrote: In the case of the MFP, it triggers a level 6 interrupt and wait for IACK from the GLUE (which is asserted when the GLUE detect an interrupt ack cycle from the CPU), it then put the interrupt vector on D0-D7 and assert DTACK. This ends up on the 68020 D24-D31 so you should assert DSACK1 in that case (16 bit transfer and the CPU know to get the 8 high bits it needs for the vector).
Regards, Rodolphe
Cheers
Stephen
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- Atari freak
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Re: Open Source 68K Accelerator Project(s)
Actually. I'm pretty sure the above is all correct because I see the CPU take the interrupt vector and execute the service routine. My strong feeling is that writes to over the synchronous bus are not being latched and therefore the MFP etc are not resetting their interrupts.
I'll double check the Interrupt vector behaviour in the simulator.
I'll double check the Interrupt vector behaviour in the simulator.
Re: Open Source 68K Accelerator Project(s)
For the 68000 CPU, the interrupt acknowledge cycle is finished when a device asserts either VPA (for an auto-vector int.), DTACK (for a non-auto-vector int.) or BERR (in which case a spurious interrupt is generated). So you distinguish the cycle by the line asserted by either the device or GLUE. You just have to translate this into the lines the 68020 expects, i.e. AVEC, DSACK.
As for your second posting: As already written, the CPU is not supposed to take the level 6 auto-vector interrupt as shown in your video but the vector indicated by the MFP. Which MFP interrupt do you see taken then?
As for your second posting: As already written, the CPU is not supposed to take the level 6 auto-vector interrupt as shown in your video but the vector indicated by the MFP. Which MFP interrupt do you see taken then?