ST vs Amiga : advantages/disadvantages

[mc6809e]

Line draws especially benefit from this technique

what about drawing lines/fills in 4 or more bitplanes? does blitter draw lines on all bitplanes at once or it needs to be restarted separately for each biplane?

While it's possible to setup a scanline interleaved display so that a regular single blit updates all planes in one operation, for area fill and line draw the blitter is usually restarted for each plane.

There are a couple of exceptions that I know of. If a line has abs(slope)>=1 and the number of planes is 4 and the display is scanline interleaved, the line pattern register can be loaded with 4 copies of the color. Then as the line is drawn, the pattern register writes the correct bits into the correct planes.

Not sure how useful that is, though.

Another exception occurs when all the bitplanes are to be written with the same bit value during area fill. Then a single blit can area fill all planes.

One way to get around the overhead associated with multiple blits/line draws is to use the COPPER. The CPU can take a COPPER list and fill it with all the register writes needed to control the blitter. Then as the COPPER is running it's program from the list, it will automatically do the writes to setup and start the blitter for one plane, execute a wait-for-blitter-finish instruction, then setup and start the next blit for the next plane, etc. The drawback with this method is that the COPPER list must finish executing by the end of the frame before it's reset to its next program. But a big benefit of this method is that you can avoid having to poll the blitter to see if it's finished for each blit. This means you can have the CPU executing other instructions while the blit/line draw/area fill is going on. Line draw skips every other cycle, so the CPU has an opportunity to do work during these skipped cycles. The alternative would be to interrupt after each blit, but interrupt handling can be expensive.

[mc6809e]

Also the last Nvidia card I bought recently, clearly states on the front of the box that it is factory overclocked! So they are fully aware of the fact people have less money to spend than they did a few years back, so pre-overclocking them is the only way to give people what they want, at a price they can afford.

That's interesting. I hadn't see that.

Another old trick is to make one chip with a large number of cores, then during testing disable those cores that don't work, selling the chips with the fewest working cores for the least money and putting higher prices on those chips with more working cores.

An NVidia GT 420 is probably just a GT 440 with fewer working cores.

[simonsunnyboy]

Also the last Nvidia card I bought recently, clearly states on the front of the box that it is factory overclocked! So they are fully aware of the fact people have less money to spend than they did a few years back, so pre-overclocking them is the only way to give people what they want, at a price they can afford.

That's interesting. I hadn't see that.

Another old trick is to make one chip with a large number of cores, then during testing disable those cores that don't work, selling the chips with the fewest working cores for the least money and putting higher prices on those chips with more working cores.

An NVidia GT 420 is probably just a GT 440 with fewer working cores.

i don't see a problem with that. It makes manufacturing easier and saves costs. And Powerusers won't buy the downgraded version anyway, and the rest does not care. I think it is ok.

[mc6809e]

Also the last Nvidia card I bought recently, clearly states on the front of the box that it is factory overclocked! So they are fully aware of the fact people have less money to spend than they did a few years back, so pre-overclocking them is the only way to give people what they want, at a price they can afford.

That's interesting. I hadn't see that.

Another old trick is to make one chip with a large number of cores, then during testing disable those cores that don't work, selling the chips with the fewest working cores for the least money and putting higher prices on those chips with more working cores.

An NVidia GT 420 is probably just a GT 440 with fewer working cores.

i don't see a problem with that. It makes manufacturing easier and saves costs. And Powerusers won't buy the downgraded version anyway, and the rest does not care. I think it is ok.

I don't see a problem with that at all, either. Whatever works!

[DarkLord]

Haven't they done the same thing with CPUs and FPUs?

[mc6809e]

Haven't they done the same thing with CPUs and FPUs?

Oh, certainly.

Binning by clock rate goes back a long time, too. If a chip doesn't work at 12.5MHz, try 10MHz. If not 10MHz, try 8MHz.

Ataris, Amigas, and Macs are full of chips designed to run at 10 MHz that would only run reliably at 8 or 7.14MHz.

I think the Mac XL was running a 68000 at 5MHz. I'm sure Motorola was happy there was someone out there to buy the worst of the lot -- at a deep discount, of course.

[Shredder11]

In case anyone is interested the factory overclocked card I bought was a ASUS GeForce GTX550 Ti DirectCU, and I got it from CCL.

[ralcool]

CPU/GPU binning is a pet peev of mine.

Lemme explain... I understand that testing often shows defects, and a solid design will allow disabling of sections in non critical areas. Like lose a bit of cache... gain a still usable chip.

Also clock speed vs temp vs stability- will vary with the quality of the 'printed/etched' silicon layers. And binned accordingly. Fine.

But... Stupid crap, like disabling hyperthreading on 'celeron' parts for example. I've met more people with a crippled Pentium4 (Celeron) than the real deal.
This is pure marketing BS. I'm sure those disabled HT parts were fine.

The 'K' series processors from Intel now... 'Unlocked and 'Unleached' they say.... ha.. No vPro, VT-d, TXT...
For example.
http://www.techeye.net/reviews/here-com ... 70k-review

Lets spend years developing a new design- and only give the good stuff to those with deep pockets- and even then you will miss out on something.
Then your Dell/HP whatevers will sell the comfortably cheapest versions of the chips to 90% of the PC normal userbase. Then your mum asks why its so slow......

Its insulting- because essentially it is the same silicon. But rarely does it get to perform to the original spec. Disabled/Cutdown marketing rubbish.

Hell IBM inserted a extra wait state to the early 286 motherboards, because they thought it was too fast for 'common' people.
Some documents suggest it was cheaper to design too.

Sorry for ranting.

Do I need to mention rare opportunities that 'hackers' find, to unlock say, the 4th core & cache of their AMD X3s, or extra 'cores' on some graphics cards.... Overclocking is the least we can do or try.
Maybe those chips had an issue, maybe the disabling of something actually had a reason.... Maybe they just were short of the cheaper/bad versions- and made some more with forced disabling of otherwise
useful parts.

ST.

[Dio]

If the premium product can't hit the premium price, the R&D for the product isn't affordable.

Using a single die for a high-end and low-end product reduces the cost of manufacture of both until the silicon area difference is quite significant (as well as the physical costs, the development and testing costs on each new type of die is astronomical) thereby improving customer value assuming the existence of an efficient market. Also note that the cost of packaging the chip can be a significant percentage of the manufacture cost, and that is probably different for different chips (e.g. a 2000-pin Xeon is a vastly more expensive package than a 775-pin Celeron) and that dies can be pad limited, so there's no value in shrinking the die below a certain point anyway.

So be careful what you wish for. The alternative is probably less capable, less efficient and more expensive.

I think we've hit a reasonably decent sweet spot right now, where the hardware stuff is mostly hard-fused off, but overclocking is tolerated and indeed somewhat encouraged for the enthusiasts.

[ralcool]

I totally accept that.

Somewhere my point was, if they can afford to sell a 'poverty/cutdown/disabled' versions of a design to the masses on purpose, then the R&D is wasted... Intel (as an example) is happy to sell MORE reduced spec parts at a lower cost- than offer everything the design mask can do for the same price- even if the best/complete version actually cost them nothing more. It is perception over reality.

The single die mask if I/You/We know anything about chip manufacturing various versions, is very common. After the initial revisions, sometimes they actually make a smaller die to suit the 'economical' market.Lose half the cache on the blueprints to improve yield and quantity in the available area, and just to annoy everyone... the base clock or FSB gets lowered too.. if for no other reason than a price point.

They sell the i5 vs the i7 (for a current example)... the difference, they turn off HT support, and in the lower models- cut the GPU core by half. There is nothing wrong with the chip. It is pure marketing.

The mobile/laptop/tablet versions tend to 'enable' better power features. Why can't my desktop PC have that too? Utter BS... and slightly maybe those chosen chips were actually a bit better during testing for low voltage/heat output. Gee, Some of us UNDERCLOCK their PCs. Can't I have, if not the better silicon, but at least the power options?, Dynamic FSB, Lower normal clock rates, but better 'Turbo' modes.

At least BMW or Lamborghini let you have the choice...(Yeah ok, for a price... )

Hardfusing sucks. I agree though... I don't need a faster processor. My Q6600 is all I need really for general use. I can overclock her- but it is useless.

I need faster internet & ethernet, a faster HDD, Better Graphics........But I really hate how CPU/GPU features can just be turned off because I didn't spend enough. And most people DON'T.
There are bigger bills to pay... We end up with a 5-6yr old PC or whatever- that is a shadow of the original idea... Slow and boring.

No flames here... Just voicing my opinion., And this is an excellent open forum to an extent. (Dal gives us significant leeway to go off topic, to just be human and talk about things)
Honestly, the moderators here are the best I've ever encountered.

ST.

Keep it real. (Intel, Nvidia, and the rest)

[mc6809e]

Somewhere my point was, if they can afford to sell a 'poverty/cutdown/disabled' versions of a design to the masses on purpose, then the R&D is wasted... Intel (as an example) is happy to sell MORE reduced spec parts at a lower cost- than offer everything the design mask can do for the same price- even if the best/complete version actually cost them nothing more.

You're missing a something very important -- that some people who can afford to pay more would pay less than they otherwise would, and that might make the difference between profitability and loss. Disabling part of a chip insures that those with deeper pockets will be forced to purchase the chip at a higher prices if they want the extra speed.

This is a kind of discriminatory pricing, and for many businesses it's essential for their survival. You've seen discriminatory pricing if you've ever bought something with a coupon that you might not otherwise have purchased at the higher price.

While discriminatory pricing sounds inherently unfair, note that governments do essentially the same thing with progressive income tax systems. They try to get those that can pay the most to pay the most.

Now I understand that you're looking to get more chip at a lower price because you can't pay full price. You might ask: what's the harm if you get a better chip but pay the same amount you normally would to Intel? The trouble is that prices would adjust as the market tries to match supply and demand. The prices of higher end chips would decline as their supply increased, but the supply of lower end chips would be reduced causing their prices to rise. Lower prices for high-end chips mean those with the deepest pockets get a discount while those with the least amount to spend may be priced out of the market.

By disabling part the of chip, Intel is causing those with the greatest ability to pay to subsidize cheaper chips for you!

[Xerus]

Reworking the numbers in terms of word accesses per frame instead of byte accesses (since the memory interface is 16 bits):

The total accesses available when all DMA is off is 71,051 words per frame. That number accounts for DMA refresh cycles. Bitplane DMA steals 5,120 word accesses/frame/bitplane for a 320x256 pal display. 4,000 accesses/frame for 320x200.

For a D channel only clear/fill, there is still no contention between the blitter and bitplane DMA for 4 or fewer bitplanes. And the blitter also doesn't conflict with 3 of 4 refresh cycles per scanline or sprites or audio DMA, so it actually gets more than half of the 71,051 mentioned above. The number is about 35,369 words per frame. This is about 70K bytes cleared per frame.

For most other common blitter operations (like copy and cookie-cut) every additional bitplane (and audio and sprites) steals from the pool of 71,051 available word accesses per frame.

For 16 color, 4 bitplane 320x200 playfield with audio: 71,051 - 16,000 - 2,504 = 52,547 words/frame available. This still compares favorably with the ST's 40,000 word accesses/frame and provides 30% more bandwidth. For cookie-cut blit, there are 13,136 writes per frame. At 16 bits/write and 4 bits/pixel that's a 52K bob/frame.

Adding hardware sprites for every scanline: 52,547 - 3200 = 49.347 words/frame. About an 6% reduction in blitter speed for most blits.

For 32 color, 5 bitplane 320x256 playfield with audio and 8 hardware sprites every scanline: 71,051 - 25,500 - 2,504 - 4,096 = 38,951 words/frame. That gives a 38K bob/frame because of the 26% speed reduction. This is slightly less than the 40,000 words/frame of the ST, but might be worth the extra colors, etc.

Do you have tested the blitter on AGA to see improvements in the Double and Quadruple mode (2 longwords or 2 double longwords with FMODE) under the same conditions?

[mc6809e]

Do you have tested the blitter on AGA to see improvements in the Double and Quadruple mode (2 longwords or 2 double longwords with FMODE) under the same conditions?

I've never used an AGA machine. I imagine the wider fetches from memory for bitplanes would open up some more cycles for the blitter (though the blitter still operates on 16 bits at a time).

[ralcool]

This is a kind of discriminatory pricing, and for many businesses it's essential for their survival. You've seen discriminatory pricing if you've ever bought something with a coupon that you might not otherwise have purchased at the higher price.
.
.
.
By disabling part the of chip, Intel is causing those with the greatest ability to pay to subsidize cheaper chips for you!

You are right... You should work as a lobbyist. lol.. damn rational thinking.

I know we're very off topic here- but you mentioned coupons. Cashback rebates in particular get right up my nose. Aside from the fact you usually have to post a coupon and a copy of a receipt back to the OEM to get your discount. It annoys the crap out of me that the taxable component of the purchase is a percentage of the retail price. So by not reducing the price at purchase time- our wonderful goverments get a few dollars more from us. Plus I'm sure manufacturer expects some people not to bother or miss a contrived deadline for their rebate.

ST.

[Dio]

So you may be getting a die with stuff turned off, but you're probably actually paying less than you would if it was a different die where the stuff didn't physically exist. I can't see an argument against that. (Or look at it this way - if it was genuinely cheaper to manufacture the chips on a different die, they would be manufactured on a different die, because it's not in the company's interests to reduce their own profit).

Don't get me wrong - having worked in the GPU industry for fifteen years I know the equation hasn't quite worked out right in the past on some products, but it's been the company's margin that takes the hit rather than the consumer's wallet, because the market dictates the price of the product - overprice at your peril, when you're limited in the ability to compete on features other than price/performance, and there are literally dozens of web sites that will benchmark your card and swoon or rage over that ratio.

[Frank B]

Reworking the numbers in terms of word accesses per frame instead of byte accesses (since the memory interface is 16 bits):

The total accesses available when all DMA is off is 71,051 words per frame. That number accounts for DMA refresh cycles. Bitplane DMA steals 5,120 word accesses/frame/bitplane for a 320x256 pal display. 4,000 accesses/frame for 320x200.

For a D channel only clear/fill, there is still no contention between the blitter and bitplane DMA for 4 or fewer bitplanes. And the blitter also doesn't conflict with 3 of 4 refresh cycles per scanline or sprites or audio DMA, so it actually gets more than half of the 71,051 mentioned above. The number is about 35,369 words per frame. This is about 70K bytes cleared per frame.

For most other common blitter operations (like copy and cookie-cut) every additional bitplane (and audio and sprites) steals from the pool of 71,051 available word accesses per frame.

For 16 color, 4 bitplane 320x200 playfield with audio: 71,051 - 16,000 - 2,504 = 52,547 words/frame available. This still compares favorably with the ST's 40,000 word accesses/frame and provides 30% more bandwidth. For cookie-cut blit, there are 13,136 writes per frame. At 16 bits/write and 4 bits/pixel that's a 52K bob/frame.

Adding hardware sprites for every scanline: 52,547 - 3200 = 49.347 words/frame. About an 6% reduction in blitter speed for most blits.

For 32 color, 5 bitplane 320x256 playfield with audio and 8 hardware sprites every scanline: 71,051 - 25,500 - 2,504 - 4,096 = 38,951 words/frame. That gives a 38K bob/frame because of the 26% speed reduction. This is slightly less than the 40,000 words/frame of the ST, but might be worth the extra colors, etc.

Do you have tested the blitter on AGA to see improvements in the Double and Quadruple mode (2 longwords or 2 double longwords with FMODE) under the same conditions?

I have. Many years ago. On the highest fmode setting you get half your bitplane DMA contention back during a blit which uses all available cycles. In low res anyway. AGA is ugly compared to the original chipset.

[1024MAK]

Err, moving from off topic to, err, off topic

Back in 1982 Sinclair (amongst others) used "half" working 64k DRAM chips to provide the top 32k RAM for the ZX Spectrum 48k...

Car makers are always producing cars with different "options" some of which are disabled for lower model cars...

And as to the MMU in the ST, in theory you could replace the DRAM with SRAM (so no refresh needed) and some selector/multiplexer chips and a lot of glue logic and then during the time that video data is not needed the Blitter could use the bus... (so MPU uses the first cycle, then the Blitter etc). Or the other way round! I don't think the Blitter could cope with being run at 16MHz to use both memory access cycles though.
But a lot of effort for not much gain this late in the ST's life

As to the style and functions offered by the ST, I think Atari did a good job when you take the price into account (remember when the STFM was launched in the UK it was competing with 8 bit micros that had built in floppy drives). It would have been nice if there had been a 64 way PCB header on the board for internal expansion and it would have been nice if the cartridge port had some extra pins so that more bus-control signals were present, so allowing more useful peripherals to be connected to this port.

I do own some Amiga machines and have played games on them. Nice machines with some very nice silicone hardware, but they do make an annoying clicking sound with their floppy drives when no disk is inserted. But I don't play games that much these days, so do not use them that much.

Mark

[mc6809e]

And as to the MMU in the ST, in theory you could replace the DRAM with SRAM (so no refresh needed) and some selector/multiplexer chips and a lot of glue logic and then during the time that video data is not needed the Blitter could use the bus... (so MPU uses the first cycle, then the Blitter etc). Or the other way round! I don't think the Blitter could cope with being run at 16MHz to use both memory access cycles though.
But a lot of effort for not much gain this late in the ST's life


As to the style and functions offered by the ST, I think Atari did a good job when you take the price into account
Mark

The trouble with static ram is the lack of density and the expense. You can put 6 times the amount of DRAM as you can static ram on the same silicon area. SRAM is big and expensive per bit compared to DRAM. And like you said, Atari did a good job on price.

It's really a shame that the MMU wasn't designed from the start to allow CPU (and later blitter) access on free odd cycles. Given the ST's clock rate of 8MHz and screen size of 200 horizontal lines, there's a ton of bandwidth available there.

Total memory accesses available per frame is 80128.
Bitplane fetches need 16000, leaving 64128.
Very aggressive refresh on remaing odd cycles takes 24064 cycles leaving 40064 accesses per frame.

The killer obviously is the aggressive DRAM memory refresh. A standard refresh should have taken about 1200 or so cycles in a frame. That leaves something like 22000 extra accesses that can't be used.

I've speculated that this aggressive refresh was used so that the system could run with slower and less expensive 150ns DRAMs that can't (technically) do back to back random memory accesses at the required 250ns for an 8MHz system (the minimum is 260ns). Those extra refresh cycles probably helped the system work at 8MHz. The alternative would have been to clock the system at a slightly slower rate like Sega Genesis that ran at 7.61 MHz.

It's possible that some instruction sequences actually run faster at 7.61MHz with access to both odd and even cycles when compared to the same sequences at 8MHz but with the even memory cycles only restriction. It probably doesn't happen very often, though.

[nativ]

Just a thought, but these 'improvements' could be worked into Aranym or possibly the FireBee, to give a new STep (STe plus) Standard?

[Frank B]

Just a thought, but these 'improvements' could be worked into Aranym or possibly the FireBee, to give a new STep (STe plus) Standard?

Long as they don't add bogo RAM support Now *that* was something that should never have seen the light of day on the Amiga!

[Cyprian]

The trouble with static ram is the lack of density and the expense. You can put 6 times the amount of DRAM as you can static ram on the same silicon area. SRAM is big and expensive per bit compared to DRAM. And like you said, Atari did a good job on price.

It's really a shame that the MMU wasn't designed from the start to allow CPU (and later blitter) access on free odd cycles. Given the ST's clock rate of 8MHz and screen size of 200 horizontal lines, there's a ton of bandwidth available there.

Total memory accesses available per frame is 80128.
Bitplane fetches need 16000, leaving 64128.
Very aggressive refresh on remaing odd cycles takes 24064 cycles leaving 40064 accesses per frame.

The killer obviously is the aggressive DRAM memory refresh. A standard refresh should have taken about 1200 or so cycles in a frame. That leaves something like 22000 extra accesses that can't be used.

I've speculated that this aggressive refresh was used so that the system could run with slower and less expensive 150ns DRAMs that can't (technically) do back to back random memory accesses at the required 250ns for an 8MHz system (the minimum is 260ns). Those extra refresh cycles probably helped the system work at 8MHz. The alternative would have been to clock the system at a slightly slower rate like Sega Genesis that ran at 7.61 MHz.

It's possible that some instruction sequences actually run faster at 7.61MHz with access to both odd and even cycles when compared to the same sequences at 8MHz but with the even memory cycles only restriction. It probably doesn't happen very often, though.

we can look at that DRAM memory refresh subject in ST from other side.
In fullscreen mode, Shifter reads 230 (115 words) bytes per line (128 memory slots): 128 - 115 = 13. It means that in ST we have 13 free slots and they can be used for memory refresh. In case of STE, DMA Sound steals some additional cycles for sample data. 50khz stereo sound needs about 3.5 cycle per line: 13 - 3 = 9; It means that in STE we have minimum 9 free cycles per line which can be used for refresh process.
ST with 13 and STE with 9 free cycles (which some of them can be used for refres) works stable. Therefore I'm not sure if phrase "the aggressive DRAM memory refresh" have place in case of ST

[1st1]

My 1040STE doesn't think that memory refresh is that important... I remember that there are programs which modify the reset pointer, so that if you press the reset button, that the system does not the normal system init, but restart that piece of software again. So sometimes I used such software, and sometimes I discovered that I could power off my STE for a few seconds, then power on again, and that software was still there.

[Dio]

I've speculated that this aggressive refresh was used so that the system could run with slower and less expensive 150ns DRAMs that can't (technically) do back to back random memory accesses at the required 250ns for an 8MHz system (the minimum is 260ns). Those extra refresh cycles probably helped the system work at 8MHz. The alternative would have been to clock the system at a slightly slower rate like Sega Genesis that ran at 7.61 MHz.

I think you're being too conspiratorial here. I think it was much simpler than that - it was simply cheaper to make every MMU access either a video access or a refresh, and the extra cycles weren't needed elsewhere and the extra power consumption on the memory wasn't important. If you want any other method you need more complicated arbitration and timing.

The Genesis clock rate is a complicated function of various dividers, and again, it's just not that important to the designers to close to 8MHz, they just want the graphics chip to work, the CPU is very much a secondary implement. It's use of VRAM makes the memory interface quite insane, it has an order of magnitude more bandwidth than the ST. I'm looking forward to getting the logic analyser on that at some point.

My 1040STE doesn't think that memory refresh is that important... I remember that there are programs which modify the reset pointer, so that if you press the reset button, that the system does not the normal system init, but restart that piece of software again. So sometimes I used such software, and sometimes I discovered that I could power off my STE for a few seconds, then power on again, and that software was still there.

It's temperature dependent. At very low temperatures retention can be measured in minutes - it's actually a security issue on some system types.

The first version of the Spectrum had a bug that meant it didn't refresh outside the screen period, and it still worked, so they didn't bother fixing it (and actually cut some circuitry out in later revs).

In the end though it comes down to - bus arbitration is complicated. A simple method like the ST's is cheap and easy to do, guarantees predictable timing and doesn't hurt performance much. It's a perfectly acceptable tradeoff. Less so once you start thinking about blitters, but by then it's too late.

[mc6809e]

I've speculated that this aggressive refresh was used so that the system could run with slower and less expensive 150ns DRAMs that can't (technically) do back to back random memory accesses at the required 250ns for an 8MHz system (the minimum is 260ns). Those extra refresh cycles probably helped the system work at 8MHz. The alternative would have been to clock the system at a slightly slower rate like Sega Genesis that ran at 7.61 MHz.

I think you're being too conspiratorial here. I think it was much simpler than that - it was simply cheaper to make every MMU access either a video access or a refresh, and the extra cycles weren't needed elsewhere and the extra power consumption on the memory wasn't important. If you want any other method you need more complicated arbitration and timing.

I don't think I've ever run into an engineer that consciously ignored chip manufacturer's signal setup/hold times without having some good reason to think they could get away with it.

But I suppose you could be right. It's also possible they simply went with the simper design intending to use 120ns DRAMs, then tried slower DRAMs later and discovered that they worked and so went with them to save money.

In the end though it comes down to - bus arbitration is complicated. A simple method like the ST's is cheap and easy to do, guarantees predictable timing and doesn't hurt performance much. It's a perfectly acceptable tradeoff. Less so once you start thinking about blitters, but by then it's too late.

I remember reading the claim that the 68000 only accessed memory every 4th CPU cycle and thinking "that's not true!" It's usually true, but not always. I really wonder how often a 68000 experiences wait states with real code in a system where it only gets to access memory on every 4th CPU cycle. I seem to remember branches/shifts/long ALU ops having timings that weren't multiples of 4. Code heavy with those ops is probably most affected.

[Dio]

I don't think I've ever run into an engineer that consciously ignored chip manufacturer's signal setup/hold times without having some good reason to think they could get away with it.

But I suppose you could be right. It's also possible they simply went with the simper design intending to use 120ns DRAMs, then tried slower DRAMs later and discovered that they worked and so went with them to save money.

I've only got timings for two old machines, the Spectrum and the ST, and they both ignore timing parameters of the memory. Dadhacker's article on the Mega ST MMU certainly implies they knew they were over the edge - he quoted one of the engineers involved was "You see, DRAMs are analogue devices really..."

I remember reading the claim that the 68000 only accessed memory every 4th CPU cycle and thinking "that's not true!" It's usually true, but not always. I really wonder how often a 68000 experiences wait states with real code in a system where it only gets to access memory on every 4th CPU cycle. I seem to remember branches/shifts/long ALU ops having timings that weren't multiples of 4. Code heavy with those ops is probably most affected.

I'll run something on Emu later and get the wait state figures. It's surprising how little it can matter - on the Spectrum, during the visible screen 6 out of every 8 memory accesses are contended for nearly 50% of the time, but it only costs about 350k, 10% or so, wait states running Jetpac (entirely from the contended bank).