68020 and AN944

Troubles with your machine? Just want to speak about the latest improvements? This is the place!

Moderators: Mug UK, Zorro 2, spiny, Greenious, Moderator Team

Post Reply
User avatar
Arne
Atari Super Hero
Atari Super Hero
Posts: 746
Joined: Thu Nov 01, 2007 10:01 am

68020 and AN944

Post by Arne »

I've been digging through Motorola's AN944 http://bitsavers.org/components/motorol ... 14p%5d.pdf lately and stumbled accross a feature I don't understand. Maybe someone can shed some light on it.

My question is about the handling of synchronous MC6800 bus cycles that have to be emulated by the board logic (pg.4 and 5 of AN944).
PAK68 and PAK68/2 (did not look into the PAK68/3) do it the same way so I assume it's not a typo/copy&paste error as it works on these PAKs.
Both 6850 ACIA's are connected to D[8..15] of the 68000 on the ST so all ACIA (8bit) registers are located on even addresses. Also the D[0..15] data-bus is connected to the 68020's D[16..31]. That's understood.
Now if the 020 wants to read an ACIA register then the read access can be triggered by some move.b ACIAREG,D0. The 020 will expect the 8bit data to be delivered on its D[24..31] and this should be acknowledged by /DSACK[1] = HI and /DSACK[0] = LO.
But it is not. As can be seen on the schematic of pg.8 of AN944 DSACK0 is only connected to the FPU and board-logic can only assert DSACK1.
Both aforementioned PAKs assert /DSACK1 in case of MC6800 cycles, too. Board-logic acknowledges these cycles with /DSACK[1] = LO and /DSACK[0] = HI i.e. a 16bit access is ack'ed for an 8bit read/write.
So I obviously miss something here. But what?

Thanks, Arne
Image
czietz
Hardware Guru
Hardware Guru
Posts: 1501
Joined: Tue May 24, 2016 6:47 pm

Re: 68020 and AN944

Post by czietz »

I'm not sure I even understand your confusion. Why do you think it would be wrong to signal a 16 bit port to 68020 in this situation? In fact, it must be done this way: the 68000 does not even support dynamic bus sizing; therefore, it always uses a 16 bit port, also with 8 bit peripherals.
User avatar
Arne
Atari Super Hero
Atari Super Hero
Posts: 746
Joined: Thu Nov 01, 2007 10:01 am

Re: 68020 and AN944

Post by Arne »

I assumed that the 020 sets its SIZ pins to read 8bit and the board-logic acknowledges with a 16bit DSACK or in other word: the 020 wants 8bit and it gets 16bit. My guess was that this should not happen. But with /DTACK only 16bit can be ack'ed. So if this does not confuse the 020 then it's okay for me. Thanks!
Image
czietz
Hardware Guru
Hardware Guru
Posts: 1501
Joined: Tue May 24, 2016 6:47 pm

Re: 68020 and AN944

Post by czietz »

It is even required. If you have a look at the 68020 UM, you can see that you have to signal a 16 bit port so that bytes at even addresses are read from/written to D31-D24 and bytes from odd addresses are read from/written to D23-D16.
68020um.PNG
You do not have the required permissions to view the files attached to this post.
User avatar
Arne
Atari Super Hero
Atari Super Hero
Posts: 746
Joined: Thu Nov 01, 2007 10:01 am

Re: 68020 and AN944

Post by Arne »

Now you confuse me. Doesn't the same table state that 8bit data is always transferred on D24..D31 independent of even/odd addresses?
ACIAs registers are on even addresses in the ST. Or do you mean that it is saver to always ack 16bit transfers for Atari/Amiga/Mac/whatever like "One size fits all" as neither the AN944 nor any PAK is specifically tailored to the ST?
Image
czietz
Hardware Guru
Hardware Guru
Posts: 1501
Joined: Tue May 24, 2016 6:47 pm

Re: 68020 and AN944

Post by czietz »

Arne wrote: Sat May 15, 2021 10:54 am Now you confuse me. Doesn't the same table state that 8bit data is always transferred on D24..D31 independent of even/odd addresses?
Only if you signal an 8 bit port (by asserting /DSACK0). This is why you don't do that. You have to always assert /DSACK1; thus signalling a 16 bit port to the CPU. In that way you stay compatible to the 68000 where even addresses are on the upper half of the bus, while odd addresses are on the lower half.
68020um-wordsized-port.png
You do not have the required permissions to view the files attached to this post.
User avatar
MasterOfGizmo
Atari God
Atari God
Posts: 1350
Joined: Fri Feb 08, 2013 12:15 pm
Contact:

Re: 68020 and AN944

Post by MasterOfGizmo »

I think the confusion comes from the fact that there are two widths involved.

You have a) the width of the data to be transferred and b) the width of the bus. The 68020 can handle all combinations of these as it supports 8, 16 and 32 bit bus widths and 8, 16 and 32 wide data transfers

The 68000 could only do 16 bit bus widths and it did not support 8 bit bus width at all. So the ST is using a 16 bit bus even for 8 bit transfers.

The big difference when doing 8 bit transfers over the different bus widths is where on the wider bus those 8 bits are passed. And that's exactly what's confusing you here. The 68020 needs to be told to use a 16 bit bus even for 8 bit transfers to behave like the 68000 to make sure the bytes use the correct 8 bits of the bus which are either d24 to 31 or d16 to 23 depending on odd/even addresses.
MIST board, FPGA based Atari STE and more: https://github.com/mist-devel/mist-board/wiki
User avatar
Arne
Atari Super Hero
Atari Super Hero
Posts: 746
Joined: Thu Nov 01, 2007 10:01 am

Re: 68020 and AN944

Post by Arne »

I understand that 8bit transfers to/from odd addresses need to be disguised as 16bit transfers as the 020 expects the 8bit data on D24..31 but actually will get them on D16..23.
But I don't understand why 8bit transfers to/from even addresses must be disguised as 16bit transfers, too. 020 expects them on D24..31 and will get them on D24..31.
Image
czietz
Hardware Guru
Hardware Guru
Posts: 1501
Joined: Tue May 24, 2016 6:47 pm

Re: 68020 and AN944

Post by czietz »

But then why would you want to unnecessarily complicate things by differentiating between even and odd addresses? Just always signaling a 16 bit port is sufficient in all cases.
Post Reply

Return to “Hardware”