Black lines between colours (demo effect)

[simbo]

lol

i see a design bug and a definate design error correct me if im wrong
accross the whole platform

there is the need for two 10k pullup resistor on the !load data pin11 of the shifter and or gst shifter
and also its !CS pin38
they are missing right from the connections from the stb/glue

so these pins are active when the chip starts up {a bad move will occur} im sure

they should be pulled up from before clock startup {a few us after power up}
st 32mhz clock there will be atleast 4 cycles of 32mhz to activly produce clocks at the 16mhz pin
this is enought time for the external sync control word to be missread or passed to the wrong memory location and not overwritten by the program
and rubbish gets written to somewhere for frequency and sync etc...
as the chip will be in write mode !load and !ce from powerup

the only thing left is DE this is device enable so perhaps its input is also strange ill scope the whole stf i have open here and post the results later ...
is the device enable in charge of writes????

to cut a long story short

see below and replace the caps first on any dodge machine

[simbo]

can you press and hold reset and boot the machine from the power with no disk in
then let go reset and click in the disk
also... there is a need to test your reset circuit

a senaro from boot up exists where there isnt enough cold reset time {poor cap}
or enough width of a warm reset pulse again another cap they both do the same thing in st/mega land

or one or more buffers can fail to halt the cpu and reset it allowing an extra transistion to occur
at cold reset say two buffers are gone then this would be the case

and for reasons as i say caps heat thru and exibit more charge holding so a fresh boot gives a different vector
that appears random but its really thermo dynamics at work inside the caps
dry caps can do strange things the chemicals can become errosive and short the plates even in extream cases they explode
they got too tired we have all seen the sm124 when it happens and filled with cotton fibres

so you have very little time vector when this happens to especialy small value capcitors they are far more sensitive to fluid loss in terms of there value cold and warm or ever {min-max/delta t}
and not enough for every chip to init at the same time
so the clocks end up out of sync by pulses becouse tos loads then a reset is made after a first boot

if i remember the trick was to listen for an inital TU!..stop say 200ms on st from the disk then another TU and a small delay before it starts loading ste did it but it was like a STA 100ms di STA should be di STA or TU di di di on pre ste
if this is the case the main cold reset was too short

but should always be around 50ms if i remember ???

so .. please tell me if this made any differance first

delaying the boot up also
then check the floppy disk after a cold start isnt so easy except waiting a while then clicking the disk in
and not autostarting from cold or reset
---------------------------------------------------------------------------------------------------------------------------------------
// TOS-> MEMORY LOADING ISSUES BOMBS MEMORY ERROR
// ...WAIT AND IT BECOMES A WHITE SCREEN THAT BLACK BARS DANCE ABOUT ON
// STRANGE VIDEO WAKE-STATES LOADED {AS SEEN HERE}
// SYSTEM CHIPSET PROBLEMS AT FRESH STARTS /RESET PRESSES/MISSING PERFFERALS
// NO SOUND{ALSO STRANGE NOISES AFTER BAD START IN THE AUDIO /PORTS/CARTLOAD SCAN
// CANT EVEN SEE PIT FALL .. DIAGNOSIS CART ETC...
// SCSI / DMA ISSUES IN FALCONS AND TT STE INFACT MOST
// REPORT A PROBLEM THIS CURED.... HERE and aill add a mention {just a bit of fun}
--------------------------------------------------------------
CHECK THESE ELECTROLYTIC CAPS BY REPLACEMENT
----------------------------------------------------------------------------------------------------------------------------------------------
stf/m........> C2 WARM RESET TIME C7 COLD RESET TIME both 22uf orange usualy electrolytics , under the psu. {lol} .
mEgA-ST....> C3 10uf COLD WARM TIME {behind the reset button}
STE..........> C100 10uf TRIGGER C102 22uf COLD/WARM RESET TIME
mEga-STE...> C208 10uf COLD RESET TIME C218 10uf WARM RESET TIME
FALCON.....> C1 22uf COLD/WARM RESET TIME C7 0.1uf TRIGGER
this explains lots as its also under the psu and a .1 oooch
if this cap is dry or the 22 is low value then a falcon may fail to start, black screen
i think or maybe white but solid never make it out of reset
--------------------------------------------------------------------------------------------------------------

use 16volt types for all
im sure ive even had brand new boxed ataris with the same fault before ...
a batch of bad ones as especialy the orange ones are bad and the light blue dark blue was better
same for all gear with caps

you get the very same problem on video machines for arcades when the reset vector drops
below the chipsets clock->reset delay and setup threashold

same thing on amplifier inputs that are coupled by small value caps
one channel goes or fade on both they are usualy 10uf
colour monitors thats colours have drifted in amplitude the feeds from the tube driver chip
has coupling caps that feed the guns driver transistors that are maybe dry

if your bamboozled by capacitors
the type you need is radial electrolytic 16V and the value in the table if you can use 105deg types
if 85c well thats ok for a while
just ask in the local lekky hobby shop you dont need to strip the board out
simply cut them off the board a little high and solder the two cropped legs on the fresh cap carefully and quickly using a low wattage iron so as not to dislodge them fully
to the stilts

remember they have a polarity so + to + - to - minus is all thats marked on the cap and + on the board
if unsure use a felt pen and draw a line down the cap and to the board first before removing it


then you know where it was

[simbo]

further and for all st machines that use an intermixed clock for the 32mhz shifter

i think that this intermix clock is a bad move for the 16mhz clock
there is no form of filter to trap any stuff even the slightes glitch to the 16mhz clock
and the program will crash if its using crytical cycles

so running a 32mhz frequency divisor and and gating it against the 16mhz clock will clean this up also
as a small filter can be added to remove the interspace 4mhz signal only used for the shifters video im sure
{cmiiw} used to frequency modultate the shifter

or... better is one and gate and another TTL 16mhz clock osc block addin {simply easy}

here is what i mean the BPF is aband pass filter
this 16 mhz from the shifter
is anded against the ttl clock to always correct it
then and against zero to restore any problems in symetry

[simbo]

managed to find a 16mhz clock ttl on an old mac board

so i have a nice picture on my scope of the older clock and new clock with and gate and ttl clock only

and its nicer by far than the old clock
but the transistions match perfect

i used a 74HC chip and as i say the old clock block from the mac {youll find 16mhz are common and on many things}

i beleve the 16mhz clock when fixed like this will clean up the 8 and 4 mhz ones tremendiously
this circuit doesnt alter the phase allignment atall looks line and square instead of peeky and wilted at the edges and top with lots of ghosts

ill try to post images but ive a poor camera maybe someone has a digital scope for the pc and can do some
before and afters

[Nyh]

can you press and hold reset and boot the machine from the power with no disk in
then let go reset and click in the disk

First while holding the reset button notice a white display comes up. Shifter and video timing is already working now.

Conclusion: reset line does not influence wakeup of the timing circuits. 'Fixing' the reset line will not cure your wakeup problems.

Hans Wessels

[simbo]

so did you replace those two caps ?? first before shooting my test down in flames

if you reset and hold a chipset for a certain time {a cold boot disk in}
then after a reset has finished {as hold is independant to reset in st machines}

then this reset time on the reset pins gets clocked into the chips
as even a reset needs clocks to make the command then exe it accross the chips registers
and also enable the clock outputs if indeed it does to each section
so the video timing being wrongly setup it something to do with the glue not resetting long enough
ive seen this fault many times
in several machines in version vertiety and its allways these caps
so given a poor reset time frame
then the shifter wont be at the right load state from the glue when the data to its wakestate register gets loaded
from tos
when tos starts it checks a cold boots disk is there then performs a reset then checks the disk again and so on till it times out and loads gem
so the second reset is the TU stop {supervisor mode re-engaged {becouse the chips resets have just finished after tos loading and first check of the disk }
then the machine resets
i can quote from page 272-> atari ST rom -BIOS in ST internals manual rev3
so supervisor mode misses a beet and you get either a bus collusion {data goes missing control words dont setup etc etc} or a grunt from the floppy
either way it carrys on

[simbo]

i have a few old stf is people need a new glue chip i think they are rev c boards ,., if your chip has become thermaly sensative
and a few shifters if needed
this should not happen ... for sure !
the output on the first pictures bug you posted nyh

is caused by incorrect pallet data and resolution setting and it all tracks back to the reset time

the second by poor sync settings control word on top of incorrect pallet data now the first bug is also 4 four frames but the same data is there
and no vertical hysnc lock the glue provides this and also the 2mhz clock 500khz clock and load and CS signals to the shifter

remember its a logic ic if you dont supply the right time and enought to catter for 20 different chips reset needs
then it wont start at the same time slots etc etc and a cascade of effects happens

however it all could just be a gubbed glue or two

[simbo]

further

a call at boot time of the software should ..... at address $FF820A setup the sync mode and screen frequency
and also zero the pallet registers {clean screen}

if these bits get set wrong or never get set at boot becouse the glue or stb hadnt long enought of a reset pulse
and insteads starts from a kind of no reset state

then only a reset and further load and refresh would fix this both in software and hardware if needed

if you look at the first post in the topic

youll see that its in low res mode and also walks by 2 increments becouse the memory contence is walked every three microseconds by increments of 2
hence the strange black specles of now missing data

[simbo]

ok i have here infront of me a C103414-001 stfm machine
it uses a C0225912-38A fpga surface mounted as the mmu

is a TOS v1.04 6chip has space for a blitter
uses C025914-38A shifter... chip
and older gubbed dma chip type {but not relevent in tos 1.04 anyway}

the two caps are indeed under the psu in this one c2 and c7 are axial types
so easier to change

the psu in this one is a bit tired and it needs some capacitors as there plastic wrappers have begun to shrink back
its the type with the round regulator again {my old pal}
mitsumi 68-4231A

so ill service this then carry on with some pictorials for the clocks and see if this machine suffers the wakeup dilema

[Nyh]

Simbo,

I find your English a bit hard to understand:

if you reset and hold a chipset for a certain time {a cold boot disk in}
then after a reset has finished {as hold is independant to reset in st machines}

Ok, I can reset the computer. Hold a chipset? In which hand? Left or right? And for how long do I have to hold that chipset? And what is the matter with {a cold boot disk in}? Makes no sense at all!

If I press the reset button on a Mega ST pen 1 of the TL7705A will be low, this results in pin 5 of the same IC becoming low. Then the driver IC7407 will pull down the Reset line (on pin 2) and it will also pull down the Halt line on pin 4 of the same IC. Pressing the rest button will activate both Halt end Reset lines. Halt and Reset being low for 100 ms or 10 clock cycles (whichever is the shortest) will reset the 68000.

then this reset time on the reset pins gets clocked into the chips
as even a reset needs clocks to make the command then exe it accross the chips registers
and also enable the clock outputs if indeed it does to each section
so the video timing being wrongly setup it something to do with the glue not resetting long enough

Once again, the GLUE will generate the timing signals independent of the state of the reset line. The MMU has no reset line. The MMU will generate its timing signals too.

so given a poor reset time frame
then the shifter wont be at the right load state from the glue when the data to its wakestate register gets loaded
from tos

I never knew the Shifter has a wakestate register. Must be carefully hidden on all register lists out there. Or maybe, just maybe it is you talking nonsense.

when tos starts it checks a cold boots disk is there then performs a reset then checks the disk again and so on till it times out and loads gem
so the second reset is the TU stop {supervisor mode re-engaged {becouse the chips resets have just finished after tos loading and first check of the disk }

Say what? TOS does not preform resets when it is trying to read the floppy disk. By that time all chips are all initialized, GEMDOS is running by then.
To be exact, after a reset:
The CPU loads SP and PC from ROM (adresses 0 and 4).
All interrupts are disabled (move #$2700,SR)
A reset instruction is executed (processor pulls down the reset line, all hardware will initialize)
Check is done for a diagnotic cardridge
Memvalid and memval2 are tested to see whether this is a warm boot
Reset vector routines are exectuted (if resvalid has the right value)
Hardware is initialized (PSG, Shifter)
Memory is tested
Memory is cleared, system variables are set up, screen is put at the end of the free memory
Interrupt routines are enabled
GEMDOS is initialized
And then, finally, floppy disk is being read to so if there is a valid bootsector
(Omitted a lot of cartridge boot possibilities)

then the machine resets
i can quote from page 272-> atari ST rom -BIOS in ST internals manual rev3
so supervisor mode misses a beet and you get either a bus collusion {data goes missing control words dont setup etc etc} or a grunt from the floppy
either way it carrys on

Yes, that is nice but all this has NOTHING to do with the ST getting in the wrong wakeup mode. The reset line cannot change wakeup mode. Only a complete power down can.

Hans Wessels

[Nyh]

a call at boot time of the software should ..... at address $FF820A setup the sync mode and screen frequency
and also zero the pallet registers {clean screen}

if these bits get set wrong or never get set at boot becouse the glue or stb hadnt long enought of a reset pulse
and insteads starts from a kind of no reset state

As fullscreen effects are working all the registers are just working fine, even in the wrong wakeup state. You are talking complete and utter nonsense here.

then only a reset and further load and refresh would fix this both in software and hardware if needed

No, it won't. A reset will not cure the wake state problems.

youll see that its in low res mode and also walks by 2 increments becouse the memory contence is walked every three microseconds by increments of 2
hence the strange black specles of now missing data

You haven't got the faintest clue of what the problems are. This is all just plain nonsense. The black speckles only appear when you change the background color when the shifter is displaying screen memory.
At low res (and also at medium and high res) two bytes of screen memory are read by the shifter every 500 nanoseconds. Every 125 nanoseconds the shifter outputs one low res pixel.

I do not understand what you want the shifter to do every 3 micro seconds but I can be clear and simple about that. It doesn't do what ever you think it should do. 3 microseconds is 24 pixels. Nothing special is happening every 24 pixels. Something special is happening every 8 pixels (1 micro second): there is a black line over there! (Only when video mem is being read at the same time, in the borders there are no black lines.) The black lines happen because color register 0 is being written at that time (where the sprites are there are no black lines, even though color o is being written there as well).

Conclusion: black lines happen when:
1 color register 0 is being written
2 the shifter is reading video memory
3 the shifter has to display color 0
4 the ST is in the wrong wakeup state

Hans Wessels

[Nyh]

so ill service this then carry on with some pictorials for the clocks and see if this machine suffers the wakeup dilema

First try to see if there is a wakeup problem.
Can you induce the wakeup problem by causing bad resets?
Can you induce the wakeup problem by lowering PSU output levels?

If you can induce the various wakeup problems (distorted full screen and black lines in colors witch) at will what make them come and how do you solve the problem.

Hans Wessels

[simbo]

reading over the posts the first time i did
i notice your machine requires to be cold for one state and warm for another
there is a gubbed chip in the chipset
what to do is take the lid off and use a hair drier to find the issue
when it stays in mode 2 then youve found it and replace that one
its a common problem you know i think its the mmu as this goes wrong quite often
however the shifter lives in a metal box and gets quite hot
so i would try that first

if its smd fpga you have it can still be changed very easily
and confirmed gubbed using a can of freezer spray

it could be at some point your psu and or machine has become very hot
and it could be two ic's and you end up chacing your tail

my guess is mmu and shifter both have an issue with tempreture

there is several reason more i can think of
forinstance
did you check the 32mhz clock purity from cold boot
this could simply be one of the transistors in the osccilator section has developed a bad junction and fails to work till its warm
and then not very well {the amplitude is low , or distorted or spuri on the carrier etc....

an impure clock would prob stagger the divider in the shifter and possibly the mmu spits out strange data as a result
do you have a scope???? if so connect it to the 32mhz input and see what it looks like when you examine the waveform
another thing is the thru plated hole themselfs
again what i do is place a weight on the board right in the middle and test
if the issue disappears then there is a brocken thru plate connection {again a common fault}
or there could be microfractures on layer 2 or 3 of the board {inside the sandwich of the 4 layers atari pcb's have}
few tracks heat can cause this to appear randomly


this machine is fine i took apart last night i used another psu this morning and tested it

every st/f ive taken from the cupboard is fine even one of the carcus {caseless}
i put a towel over it to warm it faster

so there are many reason i can still think of why this would happen and again as its a previously identified issue
and later machines dont suffer from it i can only assume its been thought about and corrected in later series

osccilator problems stf/m common components that fail
---------------------------------------------------------------------
Q10 / Q7 /Q11 can have heat related problems produce spuri or low amplitude
L45 or L48 or L43 may have a shorted turns that will vary with tempreture and cause spuri on the 32mhz clock
dry joint on ic U38 a damaged capacitor or a cracked resistor only you can tell im afraid
i cant simulate the issue on any of my machines and the one that exibited it now works as expected warm or cold

so im out

youve heard all the ideas now its time you did some tests im aok here,,, if you need a chip sent let me know
im happy to send you what i can by post



if you dont mind trying something out then you could eliminate all the osccilators right up to the 32mhz shifter input
by using a TTL 32mhz clock can
and connect it to the shifters 32mhz input
you only need the 4mhz fm baseband for the modulator to work correctly when rgb is output
if im right then this whole section can be disabled and a TTL can used if you dont !!! use no TV or svideo etc,,, and just rgb monitors
even disable the power to it to reduce load


... the end

[simbo]

well after digging out the 32mhz ttl clock can in my falcon {is redundant in there anyway as i use a nemesis in that one}

i can confirm that the stfm functions fine with just this connected to its 32mhz shifter clock on vga monitors or mono mode
and that the clock on the 16mhz output looks a lot cleaner...
the machine is faster than normal and seems a bit more firendly

i choose to modify the one i took appart last night this is a very late edition stfm has a small modulator like the ste built to the board

so try this and that will atleast discount the main osccilator if you dont have a scope
the slightly higher frequency above 32mhz is just the passband of the baseband and can be ignored
32mhz dead is fine !!!!

C2 and C7 measure 8uf and 11uf both should be 22uf
so this accounts for the problem i have that is it wont reset but will power on reset
so ive replaced them ....and it now warm resets properly

[ijor]

Hmm, I'm afraid I don't have too much time to say all what I would like in this topic right now...

In first place, wake-up is not a "defect". The defect is in the software that is not handling the wake-up condition.

As Hans explained very well, it has nothing to do with Reset.

The Shifter color issue is not related to the wake-up we talked in the other thread. That one is a relation between GLUE and MMU, Shifter is not involved.

I haven't study yet Shifter issues in details. It appears there is a combination of "Shifter wake-up" states with clock sync problems. From some experiments done by Paulo, I would say that Shifter can sometimes exhibit metastability problems. This is probably a consequence of the bad clocking design in the ST. It is not a fault of the clocking components, it is a design issue that (apparently) can sometime produce too much clock skew.

[Stefan jL]

ok.. not a shifter probelm.

Is there a way to fix the GLU or MMU if thats the problem? Maybe just replacing them is the best way.

[Stefan jL]

Now when i read the thread again from the beginning so maybe it is likely it is a shifter problem? i dont know.. ijor dont think so?

Could it be fixed by turning the pot next to the shifter? (se pic)

[dml]

In the earliest versions of Photochrome I had to work around these 'wakeup mode' problems in the software, without knowing what it was. I figured it was a shifter clock phase issue but it wasn't clear whether it was a faulty machine of mine, a fault in some machines or a design flaw in the ST generally. Interesting to see discussions about it now and some facts surfacing

[Guest]

its a simple fact crystals drift due to atomic migration even less than 100hz can stop a game cart working or the colour/dot clock making a great pic
tuning is the way
use a frequency counter { less than 20 quid on ebay all day long and very accurate these days for a cheep price}
but the age they are now i would turn the crystal around and solder it back
and use a frequency counter and a X10 scope probe to avoid loading the circuit
to adjust all the clocks
i think most ataris ,,, from experience are NOT adjusted at all
they were trucked out not rolled
and you need to adjust the clocks every so often
my grandad adjusted his clock he built every day when he came home from work
and my mum says he could tell if you even touched it

i know it takes me a good few days to tune a radio or some ham gear up properly using a counter /sig gen ... care skill and 30years experience

its a funny thing but

the atari serivce manuals ive read all say in the first few tests
if the clock like the 32mhx TTL OR the dot clock basically isnt exact then replace it or make it right
even ttl goes wrong even by 100 or so hz is bad
i wonder why...????

[Hippy Dave]

Now when i read the thread again from the beginning so maybe it is likely it is a shifter problem? i dont know.. ijor dont think so?

Could it be fixed by turning the pot next to the shifter? (se pic)

I wouldn't adjust it because I don't believe it is the problem; even in the extremely unlikely case where it were to appear to temporarily fix the problem.

If you think that a crystal is at fault, gently tap it while observing the problem you are diagnosing... no change means try something else.

Wake up state is the best explanation (eg. floating gates, flip-flop states, clock skew, timing, bugs in cpld fpga gal pal asic).

So the best chance of fixing this machine is to replace parts until it works.

Almost forgot... look for bad solder connections and open traces on the PCB.

[calimero]

if you miss this:

http://forum.8bitchip.info/software-17/ ... lp-please/

I would say it is related to this problem. If you have time, you could do few test (you will find about test at above link).

[Guest]

ctrl alt rhtshift del once it reboots press reset wait a sec and let go
then run the demo from the floppy by placing it as autoboot
if it auto boots then do this and boot from floppy
all states are reduced to cold power on boot using this key sequence + physical reset
looking at the image its the center square not the boarder addressing thats the issue
so did you try this

lets see if the issue goes away??? i dont know why would i need to run a demo ??? when i can have a beer instead...!