SaschaFFM wrote:I wanted to check out on the Cheat-Feature of MiSTer. It appears that the site https://gamehacking.org which is linked in the MiSTer-Github as a resource has been without any content (blank page) for a couple of weeks now.
Does anybody have a link to a collection of Cheats especially for SNES and Genesis? That would be great!
It's probably because you disable scripts in your browser. For me site is working fine.
Updater script downloads all cheats as far as i know.
Okay. That's true. Havent received cheats for over a month but thought there were no new one's.
Checked the website above and its only blank and white in Germany.
Connected to Switzerland, still empty. Connected to the United states and it shows up now...
the past two official builds give me garbled screens and/or black screen after the intro logo when loading games. I just compiled a build with quartus 17.1 and that doesn't exhibit any of those problems.
So far I have setup some code in verilator (SystemVerilog), and begun adding functionality to handle the MSU_ID, MSU_STATUS and MSU_TRACK registers for both read and write. I have also started to add the code into a fork or your repository (I will make this public soon). I thought I would reach out to you now to ask a few questions before I proceed much further:
1) Are you planning or are currently working on MSU-1 support? If so, I can help, or leave you to it! Up to you!
2) If I was to add in support, I notice you have a src/chip folder containing the additional special chip implementations, along with a mapper pattern to select these chips onto the bus... I have created another chip folder (src/chip/MSU) and started to add a MSU map. Would this be your preferred method for adding in MSU functionality? Even considering it is not a real special chip?
3) Are you okay with me adding further SV to your project? Given that the majority of your code is VHDL?
Cheers,
dentnz
Hi dentnz,
1) I don't plan on making a MSU-1.
2) It doesn't matter.
3) It doesn't matter.
Slightly off topic but if anyone needs to convert VHDL -> Verilog (2001, 2009 or SystemVerilog) I worked on an automated tool to do it which uses Formality to prove it is logically identical to the VHDL. In 2001 mode it struggles with advanced use of records, particularly multidimensional arrays of them as ports but in SV mode it can handle pretty much anything. If you want something converted (Single language simulations are much faster than mixed mode) then send me a PM and I should be able to return it same day.
guvner wrote:the past two official builds give me garbled screens and/or black screen after the intro logo when loading games. I just compiled a build with quartus 17.1 and that doesn't exhibit any of those problems.
I had the same issue until I turned off Low Latency mode. Not sure why, but it seemed to help. I think there may be something wrong with the current complied build.
alexh wrote:Slightly off topic but if anyone needs to convert VHDL -> Verilog (2001, 2009 or SystemVerilog) I worked on an automated tool to do it which uses Formality to prove it is logically identical to the VHDL. In 2001 mode it struggles with advanced use of records, particularly multidimensional arrays of them as ports but in SV mode it can handle pretty much anything. If you want something converted (Single language simulations are much faster than mixed mode) then send me a PM and I should be able to return it same day.
I'm not interesting in asking for conversion, but if you will release your tool, then i would like to use it.
alexh wrote:Slightly off topic but if anyone needs to convert VHDL -> Verilog (2001, 2009 or SystemVerilog) I worked on an automated tool to do it which uses Formality to prove it is logically identical to the VHDL. In 2001 mode it struggles with advanced use of records, particularly multidimensional arrays of them as ports but in SV mode it can handle pretty much anything. If you want something converted (Single language simulations are much faster than mixed mode) then send me a PM and I should be able to return it same day.
I would also be interested in using that if you ever make it available for the use of others. I would love to convert some NES code to verilog so I could use it in verilator.
I can't release my tools. All my work is owned by my employer Toshiba. And it currently uses Synopsis Formality as the backend (although I'm looking into the free tool SymbiYosis) and licences cost $10000+. Point me to the VHDL and I'll convert the files. Depending on how many files and the complexity of the VHDL configuration file and the number/size of generics/parameters it will only take a few minutes.
alexh wrote:I can't release my tools. All my work is owned by my employer Toshiba. And it currently uses Synopsis Formality as the backend (although I'm looking into the free tool SymbiYosis) and licences cost $10000+. Point me to the VHDL and I'll convert the files. Depending on how many files and the complexity of the VHDL configuration file and the number/size of generics/parameters it will only take a few minutes.
alexh wrote:I can't release my tools. All my work is owned by my employer Toshiba. And it currently uses Synopsis Formality as the backend (although I'm looking into the free tool SymbiYosis) and licences cost $10000+. Point me to the VHDL and I'll convert the files. Depending on how many files and the complexity of the VHDL configuration file and the number/size of generics/parameters it will only take a few minutes.
If you could convert the MSX core, I would appreciate it.
Today, I tried to play Tengai Makyou Zero with the latest English translation patch, but the game doesn't start and the screen stays black. Is this fixable? That would be awesome!
It's language is SFL+ instead of the popular Verilog or VHDL... Is this core better/smaller than the existing one? I suspect the current SNES core available on MiSTer platform is more mature, as it has been polished during months by different persons. If the linked new core is small enough perhaps it's portable to MiST, but I'm not sure, as I'm not an FPGA expert...
Looks like Pgate1 ported a WIP version to MiSTer a while ago https://pgate1.at-ninja.jp/SNES_on_FPGA/ it's towards the bottom of the page. Also they have a SPC player that looks cool.
Piacenti wrote:What’s the best settings in mister.ini to reduce lag from HDMI? I’m using vsync_adjust 2, can I do something more?
The other related setting would be setting the video mode to the native resolution of your HDMI display, removing the need for any additional scaling (possibly improving display latency)
I too was messing with the SNES core (SNES_20190824.rbf) today, tried playing Batman Returns, this rom has worked for me in the past (SNES_20190627.rbf) and is exhibiting strange flickering in the graphics before going black. Audio is still playing but I can't start and eventually audio stops. Super Mario RPG & Super Punch-Out with distorted graphics (looks like tiles are misaligned), part of the intro starts then goes black. Tried the earlier 0627 release but it's doing the same thing.
Photo attached for reference.
Edit: Did a complete power cycle on the DE10 instead of hitting the reset button this whole time and the problem seemed to correct itself. Though after another power cycle, seems my DE10 is on the way out.
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I was having lots of issues with Snes core, but I've loaded the Core at least 50 times now with 824 without any graphics glitching at all.
Mister 820, 627 OS, 824 Menu - current build. Batman Returns also looking good. Are you up to date with everything?
What kind of cooling do you folks have for your boards? It seems that there's potentially some interaction between core build and temperature, so you might get different results based on ambient temperature, how long your board has been running, whether you have active cooling for the board or only a heatsink, and which release of the core you're running.
Up to you!
