FPGA SNES source (srg320)

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kitrinx
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Re: FPGA SNES source (srg320)

Post by kitrinx »

On SNES backup ram is more important than on any other console on MiSTer so far. The correct size of the backup ram is stored in the ROM header and many games (Super Metroid, Donkey Kong Country, etc) will not boot and give copy protect warnings without it being the correct size. Other games, like Zelda, will not allow you to start them without it. It's a pretty important feature. Per Vitor Vilela, normal games use up to 128kb, SA-1 games (Super mario RPG) use up to 256kb, and BSX games use up to 2mb (because they would download). Many of the best games rely on saves to be playable though. It may be best to put saves somewhere other than chip ram for future compatibility. SA-1 and other fancy expansions will likely prefer to use that ram.

The SD writing in SNES.sv is not hooked up right now and is leftover from NES.sv that was used as a template.
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Re: FPGA SNES source (srg320)

Post by Sorgelig »

I didn't say it's not important. It's just too early to think about it.
Core is very unstable and this should be solved before thinking about any features.
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Re: FPGA SNES source (srg320)

Post by Sorgelig »

original FPGA SNES board has 2 RAM chips not in vain. When on-cart acceleration chips are used, they use separate RAM chip.
So, i think this core will use both SDRAM and DDR3. Hope accelerators don't mind of slight latency of DDR3.
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Re: FPGA SNES source (srg320)

Post by srg320 »

Hello
First, sorry for my bad English.

To be honest, I never thought that my source will cause so much interest.
This is my first big project on FPGA, it is a hobby, not my work, so I hope that experienced FPGA programmers will help me, for this I published a project. The problem is that I have never seen a real SNES, I found out about SNES 3 years ago, in my country SNES, NES and Sega MD2 was not licensed (we had only China clone of NES and Sega MD2), so I compared with BSNES emulator and nocash debugger. Unfortunately I have neither SNES nor a logic analyzer, I was guided by the information on the Nesdev forum, Nocash fullsnes, official SNES documentation and etc., therefore there are inconsistencies to the original.

About my board. I make it from what I could get in China and designed it to create NES, SNES, Genesis and other emulators in the future, so I put two separate 8 bit SRAM for cartridge ROM emulation and therefore the sizes of memory chips are larger than needed for SNES.
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Re: FPGA SNES source (srg320)

Post by Sorgelig »

srg320 wrote:Hello
First, sorry for my bad English.
Nice to see you here! Do you speak Russian?

Big thanks for publishing the source! Several people made SNES cores but only you were brave to publish.
So, we are trying to port it to MiSTer and there is some progress already.
Since MiSTer board has no SRAM, we need to use either SDRAM or DDR3. Because FPGA has large BRAM amount, only CART ROM(and RAM in the future) needs to be moved to SDRAM/DDR3.

What is the working status of cart chips emulation like CX4, DSPn, and others?
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Re: FPGA SNES source (srg320)

Post by srg320 »

Sorgelig wrote:Nice to see you here! Do you speak Russian?
Of course.
Sorgelig wrote:What is the working status of cart chips emulation like CX4, DSPn, and others?
CX4, DSPn and SDD1 implemented (are present in sources), but not fully tested. Also, Top gear 3000 (DSP4) has glitches, but I think problem is not in DSPn core.
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Re: FPGA SNES source (srg320)

Post by Sorgelig »

I plan to use improved SDRAM controller which will provide random access rate equivalent to 10MHz SRAM. Currently it's used only for LHRom mapping and therefore only serves the main CPU. It's definitely enough and more than 3 times faster than CPU needs. But after adding CX4,DSPn,SDD1 will it be enough to serve these chips? If i understand correctly they access the SRAM independently using higher clock.
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Re: FPGA SNES source (srg320)

Post by vanfanel »

@srg320: I am honored to salute you, sir. You are truly a hero in several forums and on the FPGA scene: in my country, Spain, there's a BIG fuss over your core on forums, Telegram groups of several boards, etc... You did something no one had done before: create a full implementation of the SNES and make it public. You went "where no man has gone before" :)

I have several SNES consoles here. I would happily donate them so you can analyze them, decap chips or whatever. I can send them to Sorgelig or you, whoever you guys want. All the SNES consoles on my collection are yours for free to experiment. I will pay for shipment too. Just PM me and they are yours. I have PAL and NTSC machines (Europe and USA).
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Re: FPGA SNES source (srg320)

Post by Sorgelig »

vanfanel wrote: I have several SNES consoles here. I would happily donate them so you can analyze them, decap chips or whatever. I can send them to Sorgelig or you, whoever you guys want. All the SNES consoles on my collection are yours for free to experiment. I will pay for shipment too. Just PM me and they are yours. I have PAL and NTSC machines (Europe and USA).
Thanks for offer, but i don't have a special tools for decapping or analyzing the buses. So, having a real console won't change anything to me.
I think the more useful info can be taken from emulators or tech docs than from real console.
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Re: FPGA SNES source (srg320)

Post by BlockABoots »

srg320 wrote:
Sorgelig wrote:Nice to see you here! Do you speak Russian?
Of course.
Sorgelig wrote:What is the working status of cart chips emulation like CX4, DSPn, and others?
CX4, DSPn and SDD1 implemented (are present in sources), but not fully tested. Also, Top gear 3000 (DSP4) has glitches, but I think problem is not in DSPn core.
Top Gear 3000 is known as a difficult game to emulate, think only in the last few updates to SD2SNES does the game actually work now :cheers:
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Re: FPGA SNES source (srg320)

Post by srg320 »

Sorgelig wrote:I plan to use improved SDRAM controller which will provide random access rate equivalent to 10MHz SRAM. Currently it's used only for LHRom mapping and therefore only serves the main CPU. It's definitely enough and more than 3 times faster than CPU needs. But after adding CX4,DSPn,SDD1 will it be enough to serve these chips? If i understand correctly they access the SRAM independently using higher clock.
Well, I tried to abide by the original timing, so access time for cartridge ROM not more 120ns, for cartridge SRAM not more 200ns. For SDD1 and SA1 the same timing, but ROM with 16 bit data bus .
vanfanel wrote:I have several SNES consoles here. I would happily donate them so you can analyze them, decap chips or whatever. I can send them to Sorgelig or you, whoever you guys want. All the SNES consoles on my collection are yours for free to experiment. I will pay for shipment too. Just PM me and they are yours. I have PAL and NTSC machines (Europe and USA).
Wow, I would be very thankful to you.
BlockABoots wrote:Top Gear 3000 is known as a difficult game to emulate, think only in the last few updates to SD2SNES does the game actually work now
I did not know that, thanks.
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Re: FPGA SNES source (srg320)

Post by ReedSolomon »

srg320 wrote: About my board. I make it from what I could get in China and designed it to create NES, SNES, Genesis and other emulators in the future, so I put two separate 8 bit SRAM for cartridge ROM emulation and therefore the sizes of memory chips are larger than needed for SNES.
I thought your board looked pretty cool, good job on everything!

We need to set you up with a MiSTer. :wink: Do you have a patreon or paypal for people to send their thanks in monetary form?
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Re: FPGA SNES source (srg320)

Post by slowmo310 »

@srg320 Many in the community have been talking about donating to you for your awesome work. Please set up a paypal, so we can show you our appreciation :D
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Re: FPGA SNES source (srg320)

Post by EisernSchild »

@srg320: Same here ! We're all hugely impressed by your awesome work and your clean code !! Please set up a paypal to let us stock up your hardware on that way !
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Re: FPGA SNES source (srg320)

Post by MattE888 »

slowmo310 wrote:@srg320 Many in the community have been talking about donating to you for your awesome work. Please set up a paypal, so we can show you our appreciation :D
I agree! Thanks for working on this!
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Re: FPGA SNES source (srg320)

Post by syboxez »

Sorgelig wrote:
vanfanel wrote: I have several SNES consoles here. I would happily donate them so you can analyze them, decap chips or whatever. I can send them to Sorgelig or you, whoever you guys want. All the SNES consoles on my collection are yours for free to experiment. I will pay for shipment too. Just PM me and they are yours. I have PAL and NTSC machines (Europe and USA).
Thanks for offer, but i don't have a special tools for decapping or analyzing the buses. So, having a real console won't change anything to me.
I think the more useful info can be taken from emulators or tech docs than from real console.
I'm not sure if you were aware, but decaps already exist for the SNES chips (2/1/3): http://www.siliconpr0n.org/map/nintendo/. The SPC and DSP are missing, but the S-APU is there.
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Re: FPGA SNES source (srg320)

Post by oskarzer0 »

Pay-Pal, please?
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Re: FPGA SNES source (srg320)

Post by ijor »

syboxez wrote:I'm not sure if you were aware, but decaps already exist for the SNES chips (2/1/3): http://www.siliconpr0n.org/map/nintendo/. The SPC and DSP are missing, but the S-APU is there.
Unfortunately the die shots don't seem good enough for die layout reverse engineering. The magnification is not high enough and there are no delayered images at all. Delayer is a process where you remove the top layers of the die and expose the bottom ones. Otherwise is very difficult, and sometimes impossible to perform the reverse engineering. There are some delayered chips on that archive, but not in this case, at least not that I could find.
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Re: FPGA SNES source (srg320)

Post by vanfanel »

ijor wrote:
Unfortunately the die shots don't seem good enough for die layout reverse engineering. The magnification is not high enough and there are no delayered images at all. Delayer is a process where you remove the top layers of the die and expose the bottom ones. Otherwise is very difficult, and sometimes impossible to perform the reverse engineering. There are some delayered chips on that archive, but not in this case, at least not that I could find.
Do you have the equipment to do what's needed? If so, I can send you some SNES machines, too.
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Re: FPGA SNES source (srg320)

Post by brNX »

Thank you for your work @srg320 and welcome

:cheers:
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Re: FPGA SNES source (srg320)

Post by ijor »

vanfanel wrote:
ijor wrote:Unfortunately the die shots don't seem good enough for die layout reverse engineering...
Do you have the equipment to do what's needed? If so, I can send you some SNES machines, too.
Sorry, I don't. For those cases that I reverse engineered the die layout, I either used die images provided by somebody else, or either I send the chip to a lab to process the decap.
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Re: FPGA SNES source (srg320)

Post by Sorgelig »

It seems impossible for Sergey(srg320) to receive PayPal donations.
But regardless this, he will get MiSTer soon, so he will be able to port SNES by himself :)
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Re: FPGA SNES source (srg320)

Post by Dubon »

Cool. Who is sending him one?
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Re: FPGA SNES source (srg320)

Post by ReedSolomon »

Well hope we can find a way to send him a Christmas gift in exchange for the one he gave us some time in the future.
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Re: FPGA SNES source (srg320)

Post by oskarzer0 »

ReedSolomon wrote:Well hope we can find a way to send him a Christmas gift in exchange for the one he gave us some time in the future.
Maybe he prefers a bottle of vodka :lol:
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