Grant’s multi computer - Need Help

cvenditti · Post by **cvenditti** » Tue Jun 05, 2018 3:24 pm

I might give it a shot, for a first port that should be too hard, but I think this will need to run CP/M too:
https://ws0.org/building-your-own-custo ... rd-part-1/

I already got it working on the DE1 with the Z80 - CP/M configuration from Grant’s code:
(You can use HS SD card with this project unlike in Grant’s code)
https://github.com/honupata/MultiCompDE1

You can find the CP/M Disk here:
http://obsolescence.wixsite.com/obsoles ... -demo-disk

Cyril

cvenditti · Post by **cvenditti** » Fri Jun 08, 2018 5:16 pm

After 3 days of fighting it is time to call for reinforcement.
Even if it is a really small core, I can get this thing to works. I have a blank screen.

Can some please give me a hint Where/What I can fix thing.

Thank you
Cyril

Here is my repo:
https://github.com/honupata/MultiComp_MISTer

Here is some code:

MultiComp.sv

Code: Select all

//============================================================================
//  Grant’s multi computer
// 
//  Port to MiSTer.
//
//  Based on Grant’s multi computer
//  http://searle.hostei.com/grant/
//  http://searle.hostei.com/grant/Multicomp/index.html
//	 and WiSo's collector blog (MiST port)
//	 https://ws0.org/building-your-own-custom-computer-with-the-mist-fpga-board-part-1/
//	 https://ws0.org/building-your-own-custom-computer-with-the-mist-fpga-board-part-2/
//
//  This program is free software; you can redistribute it and/or modify it
//  under the terms of the GNU General Public License as published by the Free
//  Software Foundation; either version 2 of the License, or (at your option)
//  any later version.
//
//  This program is distributed in the hope that it will be useful, but WITHOUT
//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
//  more details.
//
//  You should have received a copy of the GNU General Public License along
//  with this program; if not, write to the Free Software Foundation, Inc.,
//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================


module emu
(
	//Master input clock
	input         CLK_50M,

	//Async reset from top-level module.
	//Can be used as initial reset.
	input         RESET,

	//Must be passed to hps_io module
	inout  [44:0] HPS_BUS,

	//Base video clock. Usually equals to CLK_SYS.
	output        CLK_VIDEO,

	//Multiple resolutions are supported using different CE_PIXEL rates.
	//Must be based on CLK_VIDEO
	output        CE_PIXEL,

	//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
	output  [7:0] VIDEO_ARX,
	output  [7:0] VIDEO_ARY,

	output  [7:0] VGA_R,
	output  [7:0] VGA_G,
	output  [7:0] VGA_B,
	output        VGA_HS,
	output        VGA_VS,
	output        VGA_DE,    // = ~(VBlank | HBlank)

	output        LED_USER,  // 1 - ON, 0 - OFF.

	// b[1]: 0 - LED status is system status OR'd with b[0]
	//       1 - LED status is controled solely by b[0]
	// hint: supply 2'b00 to let the system control the LED.
	output  [1:0] LED_POWER,
	output  [1:0] LED_DISK,

	output [15:0] AUDIO_L,
	output [15:0] AUDIO_R,
	output        AUDIO_S,   // 1 - signed audio samples, 0 - unsigned
	output  [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
	input         TAPE_IN,

	// SD-SPI
	output        SD_SCK,
	output        SD_MOSI,
	input         SD_MISO,
	output        SD_CS,
	input         SD_CD,

	//High latency DDR3 RAM interface
	//Use for non-critical time purposes
	output        DDRAM_CLK,
	input         DDRAM_BUSY,
	output  [7:0] DDRAM_BURSTCNT,
	output [28:0] DDRAM_ADDR,
	input  [63:0] DDRAM_DOUT,
	input         DDRAM_DOUT_READY,
	output        DDRAM_RD,
	output [63:0] DDRAM_DIN,
	output  [7:0] DDRAM_BE,
	output        DDRAM_WE,

	//SDRAM interface with lower latency
	output        SDRAM_CLK,
	output        SDRAM_CKE,
	output [12:0] SDRAM_A,
	output  [1:0] SDRAM_BA,
	inout  [15:0] SDRAM_DQ,
	output        SDRAM_DQML,
	output        SDRAM_DQMH,
	output        SDRAM_nCS,
	output        SDRAM_nCAS,
	output        SDRAM_nRAS,
	output        SDRAM_nWE
);

assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;

assign AUDIO_S   = 1;
assign AUDIO_MIX = status[3:2];

assign LED_USER  = 0;
assign LED_DISK  = 0;
assign LED_POWER = 0;

assign VIDEO_ARX = status[5:4] ? 8'd16 : 8'd4;
assign VIDEO_ARY = status[5:4] ? 8'd9  : 8'd3;

localparam CONF_BDI   = "(BDI)";
localparam CONF_PLUSD = "(+D) ";
localparam CONF_PLUS3 = "(+3) ";

`include "build_id.v"
localparam CONF_STR = {
	"MultiComp;;"
};


////////////////////   CLOCKS   ///////////////////

assign CLK_VIDEO = clk_sys;

wire locked;
wire clk_sys;

pll pll
(
	.refclk(CLK_50M),
	.rst(0),
	.outclk_0(clk_sys),
	.outclk_1(SDRAM_CLK),
	.locked(locked)
);

//////////////////   HPS I/O   ///////////////////
wire [15:0] joy_0;
wire [15:0] joy_1;
wire [15:0] joya_0;
wire [15:0] joya_1;
wire  [1:0] buttons;
wire [31:0] status;
wire [24:0] ps2_mouse;

wire PS2_CLK;
wire PS2_DAT;

wire forced_scandoubler;

wire [31:0] sd_lba;
wire        sd_rd;
wire        sd_wr;
wire        sd_ack;
wire  [8:0] sd_buff_addr;
wire  [7:0] sd_buff_dout;
wire  [7:0] sd_buff_din;
wire        sd_buff_wr;
wire        img_mounted;
wire        img_readonly;
wire [63:0] img_size;
wire        sd_ack_conf;

hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
(
	.clk_sys(clk_sys),
	.HPS_BUS(HPS_BUS),

	.conf_str(CONF_STR),

	.joystick_0(joy_0),
	.joystick_1(joy_1),
	.joystick_analog_0(joya_0),
	.joystick_analog_1(joya_1),

	.buttons(buttons),
	.status(status),
	.forced_scandoubler(forced_scandoubler),

	.ps2_kbd_clk_out(PS2_CLK),
	.ps2_kbd_data_out(PS2_DAT),
	
	.ps2_kbd_led_use(0),
	.ps2_kbd_led_status(0),

	.ps2_mouse(ps2_mouse),

	.sd_lba(sd_lba),
	.sd_rd(sd_rd),
	.sd_wr(sd_wr),
	.sd_ack(sd_ack),
	.sd_ack_conf(sd_ack_conf),
	.sd_buff_addr(sd_buff_addr),
	.sd_buff_dout(sd_buff_dout),
	.sd_buff_din(sd_buff_din),
	.sd_buff_wr(sd_buff_wr),
	.img_mounted(img_mounted),
	.img_readonly(img_readonly),
	.img_size(img_size),

	.ioctl_wait(0)
);

Microcomputer Microcomputer(
		.RESET_N(RESET),
		.SDRAM_nCS(SDRAM_nCS),
		.VGA_R(VGA_R),
		.VGA_G(VGA_G),
		.VGA_B(VGA_B),
		.VGA_HS(VGA_HS),
		.VGA_VS(VGA_VS),
		.ps2_clk(PS2_CLK),
		.ps2_data(PS2_DAT),
);

endmodule
.

Microcomputer.vhd

Code: Select all

-- This file is copyright by Grant Searle 2014
-- You are free to use this file in your own projects but must never charge for it nor use it without
-- acknowledgement.
-- Please ask permission from Grant Searle before republishing elsewhere.
-- If you use this file or any part of it, please add an acknowledgement to myself and
-- a link back to my main web site http://searle.hostei.com/grant/    
-- and to the "multicomp" page at http://searle.hostei.com/grant/Multicomp/index.html
--
-- Please check on the above web pages to see if there are any updates before using this file.
-- If for some reason the page is no longer available, please search for "Grant Searle"
-- on the internet to see if I have moved to another web hosting service.
--
-- Grant Searle
-- eMail address available on my main web page link above.

library ieee;
use ieee.std_logic_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;

entity Microcomputer is
	port(
		RESET_N 		: in std_logic;
		SDRAM_nCS	: out std_logic;

		VGA_R  	 	: out std_logic_vector(5 downto 0); --std_logic_vector(7 downto 0); ?
		VGA_G    	: out std_logic_vector(5 downto 0); --std_logic_vector(7 downto 0); ?
		VGA_B   		: out std_logic_vector(5 downto 0); --std_logic_vector(7 downto 0); ?

		VGA_HS		: out std_logic;
		VGA_VS		: out std_logic;

		ps2_clk		: out std_logic;
		ps2_data		: out std_logic
	);
end Microcomputer;

architecture struct of Microcomputer is
	signal n_reset						: std_logic;-- :='1';
	signal clk							: std_logic;
	signal n_WR							: std_logic;
	signal n_RD							: std_logic;
	signal cpuAddress					: std_logic_vector(15 downto 0);
	signal cpuDataOut					: std_logic_vector(7 downto 0);
	signal cpuDataIn					: std_logic_vector(7 downto 0);

	signal basRomData					: std_logic_vector(7 downto 0);
	signal internalRam1DataOut		: std_logic_vector(7 downto 0);
	signal internalRam2DataOut		: std_logic_vector(7 downto 0);
	signal interface1DataOut		: std_logic_vector(7 downto 0);
	signal interface2DataOut		: std_logic_vector(7 downto 0);
	signal sdCardDataOut				: std_logic_vector(7 downto 0);

	signal n_memWR						: std_logic :='1';
	signal n_memRD 					: std_logic :='1';

	signal n_ioWR						: std_logic :='1';
	signal n_ioRD 						: std_logic :='1';

	signal n_MREQ						: std_logic :='1';
	signal n_IORQ						: std_logic :='1';	

	signal n_int1						: std_logic :='1';	
	signal n_int2						: std_logic :='1';	

	signal n_externalRamCS			: std_logic :='1';
	signal n_internalRam1CS			: std_logic :='1';
	signal n_internalRam2CS			: std_logic :='1';
	signal n_basRomCS					: std_logic :='1';
	signal n_interface1CS			: std_logic :='1';
	signal n_interface2CS			: std_logic :='1';
	signal n_sdCardCS					: std_logic :='1';

	signal serialClkCount			: std_logic_vector(15 downto 0);
	signal cpuClkCount				: std_logic_vector(5 downto 0); 
	signal sdClkCount					: std_logic_vector(5 downto 0); 	
	signal cpuClock					: std_logic;
	signal serialClock				: std_logic;
	signal sdClock						: std_logic;

	signal ps2Clk						: std_logic;
	signal ps2Data						: std_logic;

	signal switches       : std_logic_vector(1 downto 0);
	signal buttons        : std_logic_vector(1 downto 0);
	signal r1 : std_logic;
	signal r2 : std_logic;
	signal g1 : std_logic;
	signal g2 : std_logic;
	signal b1 : std_logic;
	signal b2 : std_logic;
	
begin
  
-- ____________________________________________________________________________________
-- CPU CHOICE GOES HERE
cpu1 : entity work.t80s
  generic map(mode => 1, t2write => 1, iowait => 0)
  port map(
	  RESET_N => n_reset,
	  clk_n => cpuClock,
	  wait_n => '1',
	  int_n => '1',
	  nmi_n => '1',
	  busrq_n => '1',
	  mreq_n => n_MREQ,
	  iorq_n => n_IORQ,
	  rd_n => n_RD,
	  wr_n => n_WR,
	  a => cpuAddress,
	  di => cpuDataIn,
	  do => cpuDataOut
	 );

-- ____________________________________________________________________________________
-- ROM GOES HERE	
rom1 : entity work.Z80_BASIC_ROM -- 8KB BASIC
  port map(
	  address => cpuAddress(12 downto 0),
	  clock => clk,
	  q => basRomData
	);
	
-- ____________________________________________________________________________________
-- RAM GOES HERE
ram1: entity work.InternalRam4K
	port map
	(
		address => cpuAddress(11 downto 0),
		clock => clk,
		data => cpuDataOut,
		wren => not(n_memWR or n_internalRam1CS),
		q => internalRam1DataOut
	);

-- ____________________________________________________________________________________
-- INPUT/OUTPUT DEVICES GO HERE	

io1 : entity work.SBCTextDisplayRGB
	port map (
		n_reset => n_reset,
		clk => clk,

		-- RGB video signals
		hSync => VGA_HS,
		vSync => VGA_VS,
		videoR0 => r1,
		videoR1 => r2,
		videoG0 => g1,
		videoG1 => g2,
		videoB0 => b1,
		videoB1 => b2,

		n_wr => n_interface1CS or n_ioWR,
		n_rd => n_interface1CS or n_ioRD,
		n_int => n_int1,
		regSel => cpuAddress(0),
		dataIn => cpuDataOut,
		dataOut => interface1DataOut,
		ps2Clk => ps2Clk,
		ps2Data => ps2Data
	);

VGA_R <= (r1,r2,r1,r2,r1,r2);
VGA_G <= (g1,g2,g1,g2,g1,g2);
VGA_B <= (b1,b2,b1,b2,b1,b2);

-- ____________________________________________________________________________________
-- MEMORY READ/WRITE LOGIC GOES HERE
n_ioWR <= n_WR or n_IORQ;
n_memWR <= n_WR or n_MREQ;
n_ioRD <= n_RD or n_IORQ;
n_memRD <= n_RD or n_MREQ;

-- ____________________________________________________________________________________
-- CHIP SELECTS GO HERE
n_basRomCS <= '0' when cpuAddress(15 downto 13) = "000" else '1'; --8K at bottom of memory
n_interface1CS <= '0' when cpuAddress(7 downto 1) = "1000000" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 2 Bytes $80-$81
n_sdCardCS <= '0' when cpuAddress(7 downto 3) = "10001" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 8 Bytes $88-$8F
n_internalRam1CS <= '0' when cpuAddress(15 downto 12) = "0010" else '1';

-- ____________________________________________________________________________________
-- BUS ISOLATION GOES HERE
cpuDataIn <=
interface1DataOut when n_interface1CS = '0' else
basRomData when n_basRomCS = '0' else
internalRam1DataOut when n_internalRam1CS= '0' else
x"FF";

-- ____________________________________________________________________________________
-- SYSTEM CLOCKS GO HERE
-- SUB-CIRCUIT CLOCK SIGNALS
serialClock <= serialClkCount(15);
	process (clk)
	begin
		if rising_edge(clk) then

			if cpuClkCount < 4 then -- 4 = 10MHz, 3 = 12.5MHz, 2=16.6MHz, 1=25MHz
				cpuClkCount <= cpuClkCount + 1;
			else
				cpuClkCount <= (others=>'0');
			end if;
			if cpuClkCount < 2 then -- 2 when 10MHz, 2 when 12.5MHz, 2 when 16.6MHz, 1 when 25MHz
				cpuClock <= '0';
			else
				cpuClock <= '1';
			end if;

			if sdClkCount < 49 then -- 1MHz
				sdClkCount <= sdClkCount + 1;
			else
				sdClkCount <= (others=>'0');
			end if;
			if sdClkCount < 25 then
				sdClock <= '0';
			else
			sdClock <= '1';
			end if;

			-- Serial clock DDS
			-- 50MHz master input clock:
			-- Baud Increment
			-- 115200 2416
			-- 38400 805
			-- 19200 403
			-- 9600 201
			-- 4800 101
			-- 2400 50
			serialClkCount <= serialClkCount + 2416;
		end if;
	end process;
end;

GreyRogue · Post by **GreyRogue** » Fri Jun 08, 2018 6:03 pm

Did you hook up CE_PIXEL anywhere?

cvenditti · Post by **cvenditti** » Fri Jun 08, 2018 6:50 pm

GreyRogue wrote:Did you hook up CE_PIXEL anywhere?

Thank you for the suggestion

I just added

Code: Select all

assign CE_PIXEL = 1;

Unfortunately I still have a blank screen.

Thank you
Cyril

GreyRogue · Post by **GreyRogue** » Fri Jun 08, 2018 8:12 pm

Are your clocks configured correctly? SBCTextDisplayRGB looks like it's set up for 50MHz, but I think your clocks are set to 112 MHz. Even with 50 I think your pixel clock is 25 MHz, so you need to fix CE_PIXEL.

cvenditti · Post by **cvenditti** » Fri Jun 08, 2018 8:33 pm

GreyRogue wrote:Are your clocks configured correctly? SBCTextDisplayRGB looks like it's set up for 50MHz, but I think your clocks are set to 112 MHz. Even with 50 I think your pixel clock is 25 MHz, so you need to fix CE_PIXEL.

Yes, you are right I changed the main clock. is no video but the screen is not going to sleep now.

Thank you
Cyril

brunosilva · Post by **brunosilva** » Sat Feb 02, 2019 8:47 pm

hi

not possible to use vhd and not a secondary sd card?

Thanks

djmartins · Post by **djmartins** » Wed Feb 06, 2019 5:11 am

I have this core working with that demo disk written to the secondary SD card.
Been playing the Colossal Cave 550 point Adventure on that disk.

ex68k · Post by **ex68k** » Thu Feb 07, 2019 2:07 pm

djmartins wrote:I have this core working with that demo disk written to the secondary SD card.
Been playing the Colossal Cave 550 point Adventure on that disk.

Could we move it to the MISTer repository?

cvenditti · Post by **cvenditti** » Thu Feb 07, 2019 3:32 pm

I did a quick implementation myself but I can only have it working in read not write.

MultiComp_MiSTer-master.zip

see http://www.atari-forum.com/viewtopic.ph ... sd#p359133

If I remember correctly you just have to rename the image "MultiComp.VHD"

To test the write you can try with a command like "PIP B:=C:MBASIC.com". For me the system hang indefinitely.

Let me know if someone can fix it.
Thanks
Cyril

ex68k wrote:
djmartins wrote:I have this core working with that demo disk written to the secondary SD card.
Been playing the Colossal Cave 550 point Adventure on that disk.
Could we move it to the MISTer repository?

djmartins · Post by **djmartins** » Thu Feb 07, 2019 3:50 pm

cvenditti wrote:I did a quick implementation myself but I can only have it working in read not write. MultiComp_MiSTer-master.zip
see http://www.atari-forum.com/viewtopic.ph ... sd#p359133

If I remember correctly you just have to rename the image "MultiComp.VHD"

To test the write you can try with a command like "PIP B:=C:MBASIC.com". For me the system hang indefinitely.

Let me know if someone can fix it.
Thanks
Cyril

ex68k wrote:
djmartins wrote:I have this core working with that demo disk written to the secondary SD card.
Been playing the Colossal Cave 550 point Adventure on that disk.
Could we move it to the MISTer repository?

I am able to write a save game for Adventure so it writes.
Using the latest release Multicomp RBF writing the image to an sdcard.
Try that, not putting a vhd image on the sdcard.

Are you using the USB console to see if there are any error messages?

cvenditti · Post by **cvenditti** » Thu Feb 07, 2019 3:57 pm

djmartins wrote: I am able to write a save game for Adventure so it writes.
Using the latest release Multicomp RBF writing the image to an sdcard.
Try that, not putting a vhd image on the sdcard.
Are you using the USB console to see if there are any error messages?

I might not understand correctly what you are saying

Yes if you write the image to the second SD card everything works but for convenience purpose the goal is to use a VHD image on the second SD card.
Not to have any needs to change the SD card between cores.

djmartins · Post by **djmartins** » Thu Feb 14, 2019 12:39 am

cvenditti wrote:
djmartins wrote: I am able to write a save game for Adventure so it writes.
Using the latest release Multicomp RBF writing the image to an sdcard.
Try that, not putting a vhd image on the sdcard.
Are you using the USB console to see if there are any error messages?
I might not understand correctly what you are saying
Yes if you write the image to the second SD card everything works but for convenience purpose the goal is to use a VHD image on the second SD card.
Not to have any needs to change the SD card between cores.

It never worked for me, I had to write the image to the sdcard.

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