MiSTer on DE10-Standard - needed?

[Sorgelig]

Terasic is selling another board - DE10-standard: http://www.terasic.com.tw/cgi-bin/page/ ... 1&PartNo=1
From MiSTer point of view it's pretty the same as DE10-nano:

+ Size of FPGA and DDR3 are the same.
+ It has SDRAM on board
+ Has VGA and analog audio on board
+ Full size USB host connectors
- No HDMI
- It's more than twice larger board, so definitely not for minimalists
- Much more expensive

VGA on this board can be used with scaler(can be switchable original/scaler) - just the same as HDMI. For HDMI, external $5 VGA-HDMI converter can be used since VGA output will have correct VGA/HD resolutions (not like VGA on MiST).

Some people complain that MiSTer is not a turn-key solution for end-user as it requires soldering the addons or search where to buy. DE10-standard can be that turn-key solution, as it won't have required addons, although some options like RTC can be added. It's probably twice more expensive than DE10-nano with all add-on boards attached. But i've heard opinions that price doesn't matter.

Since board is at 99% the same resource-wise with DE10-nano, it will be pretty simple to port the cores. Linux part will be identical. Although every core should be specifically compiled for this board.
I'm not really convinced in this fork, as i think DE10-standard has no that charm of tiny mighty DE10-nano.

Just wanna hear opinion from potential users. It's just in very beginning evaluation stage. I even have no this board. I still have long todo list for MiSTer. If someone else will do the port, then i would be just glad

[alfishe]

Terasic is selling another board - DE10-standard: http://www.terasic.com.tw/cgi-bin/page/ ... 1&PartNo=1
From MiSTer point of view it's pretty the same as DE10-nano:

DE10-Standard + HDMI output FMSC card combo looks weird from user standpoint and cover significant area on a table. So... as a devkit it brings almost nothing except stable speed SDRAM and lack of HDMI can be treated as significant flaw nowadays.

Let's port MiSTer to uber-killah! https://www.digikey.com/product-detail/ ... ND/7100530 =))

[olin]

For me DE10-standard is too expensive, but there is the DE1-Soc which has almost the same specs as DE10-standard ('only' 85k of LE) and is $100 cheaper. I'm happy with my DE0ns at the moment, but the VGA scaler would be handy (not that I could compile non-lite version of it anyway...)

[ijor]

Arguably the nano has more bang for the buck, but the DE-10 Standard is a fabulous board. The FPGA is faster than the one on the nano (C6 vs I7) and slightly more powerful (the transceiver variant). It includes also some other goodies such a high speed HSMC connector, a small LCD, 7-segment displays, IR, video input, etc. It is also runs cooler (in the literal sense ).

For those that don't mind the price and prefer a turn key solution it's just great. Yes, the DE-10 SOC is another option.

[alfishe]

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[alfishe]

If it's another speed grade and other parameters - so twice harder to support as a platform...

[Newsdee]

It might be worth it to port MiSTer to it just because of longevity, i.e. between this, the DE10-Nano-SoC and DE0-Nano there is a good chance the cores will remain playable for a very long time even if one or two boards stop being produced. It also opens more options for people buying their board on the second hand market. And I like the fact of having a board that works without add-ons, which is one common concern with the MiSTer as it stands today (at least until a stable assembled PCB seller shows up).

Also judging from Terasic's page and all the faces of professors backing the board, I assume it might be a common board bought by students. That's more potential new blood to write, port and maintain cores The slight paradigm shift would be of thinking about MiSTer as a Framework to run cores instead of being specific to one single board. That would be a strong unifying force in retro gaming hardware.

Of course I say all this assuming that the work to port is not difficult and not too long; otherwise it's more to maintain overall.

[ijor]

If it's another speed grade and other parameters - so twice harder to support as a platform...

Not at all. The FPGA difference doesn't make it any harder. There are no parameters to change for that. Quartus would take care automatically and you have to recompile anyway because the pinout is different.

The faster speed grade certainly doesn't even require a recompile. If everything else would be the same (say, upgrading a DE-10 nano to a -6 speed grade), then you could use the same binary without any problems.

[Sorgelig]

Lessons from ijor are unavoidable

If everything else would be the same (say, upgrading a DE-10 nano to a -6 speed grade), then you could use the same binary without any problems.

except that DE10-nano is Cyclone V SE, while DE10-standard is Cyclone V SX

DE10-Standard + HDMI output FMSC card combo looks weird from user standpoint and cover significant area on a table. So... as a devkit it brings almost nothing except stable speed SDRAM and lack of HDMI can be treated as significant flaw nowadays.

HDMI daughter board is not required in this case. Cheap VGA->HDMI converter will work just fine if VGA will output let's say 1280x720p60 or 1920x1080p60.

[Sorgelig]

It might be worth it to port MiSTer to it just because of longevity, i.e. between this, the DE10-Nano-SoC and DE0-Nano there is a good chance the cores will remain playable for a very long time even if one or two boards stop being produced.

it's unnecessary with open source project as it can be done anytime. And you don't know what boards will be popular 5-6 years later. Non direct signs show that DE10-nano at least 10 times more popular than DE10-standard. I even see other manufacturers start to sell similar to DE10-nano format boards. Today with high popularity of robots with new AI and IoT, tiny form-factor of DE10-nano is more demanded that traditional large boards. Thus, DE10-nano should have much longer life, IMHO.

[Sorgelig]

but there is the DE1-Soc which has almost the same specs as DE10-standard

yes, these 2 boards are very similar to each other if you don't need high-speed transceivers. Unfortunately DE1-SoC has smaller FPGA, so not all cores will be possible to port. ao486 won't fit for example. Smaller FPGA also means smaller amount of BRAM as well - this is more crucial part than LE. All in all - it will be compromise solution.

[ijor]

If everything else would be the same (say, upgrading a DE-10 nano to a -6 speed grade), then you could use the same binary without any problems.

except that DE10-nano is Cyclone V SE, while DE10-standard is Cyclone V SX

I know, I already said above the DE-10 standard has a transceiver variant. That's precisely why I said "if everything else would be the same" by upgrading a DE-10 nano just to a faster speed grade. And not upgrading to the FPGA part that the DE-10 standard has.

My point there was only to note that a faster speed grade doesn't even require a recompile (again, as long as everything else is the same). That was just in reply to alfishe's comment that the different speed grade could be another factor that would require changing parameters or complicating the port.

[nightshadowpt]

If you could just re-use the cores from the regular MiSTer, I would not mind, but if it needs to be recompiled/maintained separately, then I'd rather not do it, as it will fracture the market even more.

[Sorgelig]

It's not really will make a fracture if code will be the same. Just project file will be different with other pin descriptions and couple defines to change something in the code.

[Newsdee]

Would it he possible to keep the code together in github, with the only changes being in the top project file? If so any improvement to cores would be easily recompilable to all.

[Sorgelig]

Would it he possible to keep the code together in github, with the only changes being in the top project file? If so any improvement to cores would be easily recompilable to all.

yes.

[Roman]

IMHO - not really needed unless DE10-Nano stops being sold. I would prefer the developers to spend time on something more useful... improving Amiga core for example

[misterjbam]

outchhhh $350 No thanks .
at this price, it's not the same thing anymore

[Sorgelig]

I'm also more close to NO, than YES.

[ijor]

I think it would be nice to implement, at least, minimal support for the DE-10 Standard, and may be also for the DE1-SOC.

Porting a couple of cores and setting the framework is not too much effort and only need to be done once. Then maintaining the support for these boards has almost zero cost. No need to port or to test every single core. Just to have the framework ready.

I mention the DE1-SOC, because once you support the DE-10 Standard, adding the DE1-SOC is almost trivial. Yeah, the ao486 core might not fit, so what? If a user wants that core then he would go for the DE-10 Standard or the Nano.

Big question is if the Kernel doesn't need to be ported. I mentioned this already in some other thread. Possibly there is no need to. But there has to be a reason why Terasic provides separate builds for each board variant. Or they just didn't realize they could share the same build???

One significant difference on the DE-10-Standard is that Linux can bootstrap, at least in theory, from Flash. But the schematics show serial flash as non populated ??? The Flash parameters do are enabled in the U-Boot.

[Sorgelig]

DE10-nano also can boot from serial flash (EPCS). There is no difference from DE10-std or DE1-SocKit here. It's not convenient because it will require a special update utility. Having everything on SD card is much easier to maintain.

I'm sure both DE1-SocKit and DE10-std can boot my linux. DE0-Sockit is proven to boot from the same SD card as DE10-nano.

[ijor]

DE10-nano also can boot from serial flash (EPCS). There is no difference from DE10-std or DE1-SocKit here.

No, it's not the same. There is no FLASH device connected to the HPS on the nano, the only serial flash available is for configuring the FPGA side. The DE-10 standard has a QSPI flash directly connected to the ARM side, that is in addition to the EPCS device for configuring the FPGA. And then the ARM on the DE-10 standard can boot from flash if selected on the dip switches setting.

At least this is according to the DE-10 Standard schematics. The layout picture (back side of the board) shows it is unpopulated though, and with a notice "DO NOT INSERT". But again, it is wired at the board and if you look at the DE-10-Std U-Boot configuration, contrary to the nano one, the settings is enabled. This is only for the DE-10-Std, the DE1-SOC doesn't have the QSPI flash.

But it is very possible that it doesn't matter anyway. In the worst case you loose the option to boot from flash. I only would like to verify what happens with those QSPI pins when they are not configured correctly. Probably nothing, at least as long as there is no populated QSPI flash device.

[Sorgelig]

Booting HPS from FPGA is standard feature of Cyclone V.
Select MSEL switches to boot FPGA from EPCS, then FPGA will be able to kick off the HPS booting from OCRAM filled by FPGA. And so on, continuing to boot from EPCS.

[alfishe]

One significant difference on the DE-10-Standard is that Linux can bootstrap, at least in theory, from Flash. But the schematics show serial flash as non populated ??? The Flash parameters do are enabled in the U-Boot.

Why the question about boot sequence and devices even came to a scene? Booting HPS from sd and then loading bitstream to FPGA is pretty reliable and convenient, also works on every SoC board.
Booting HPS from flash might be slower than with existing sequence (SoC bootloader -> U-boot and Linux from SD).
50MHz 4 data lines SD 3.0 and measured 2 seconds boot time - why do we need programming any flashes? =))

Adaptation for ITE HDMI transmitter (on daughterboard) bothers me way more. VGA-only in year 2018 - not my choice.

[ijor]

Booting HPS from FPGA is standard feature of Cyclone V.
Select MSEL switches to boot FPGA from EPCS, then FPGA will be able to kick off the HPS booting from OCRAM filled by FPGA. And so on, continuing to boot from EPCS.

I know, but once again, this is something different.

Besides being able to boot from the FPGA, and then indirectly from EPCS, the HPS can boot directly from serial flash without even configuring the FPGA at all. This is a different flash, connected to different pins that are dedicated at the HPS side, and with a different MSEL switches configuration.

All Cyclone V SOCs can boot the HPS from this flash, but only the Standard has the connection on the board (although it seems the actual device is not populated). And again, only the Standard have this enabled on U-boot.

Why the question about boot sequence and devices even came to a scene? Booting HPS from sd and then loading bitstream to FPGA is pretty reliable and convenient, also works on every SoC board.

May be I am not expressing myself correctly. I am not suggesting to boot from flash at all. I am just raising the issue because the different pinout at the HPS side, and then the different U-boot configuration, between the DE-10 Standard and the Nano.