Minimig (Amiga) core discussion

[R4MS]

I get a black picture on all monitors with composite_sync=0. Setting it to 1 works.

[pedranic]

Hi, I'm a new user of mister since yesterday, and I'm impressed with how it works.

I believe that I have correctly configured the video output for my LCD for HDMI with full hd resolution. The config is:
- scale_mode=1 (for integer scale, is how i like for pixel perfect in 1920x1080)
- video_mode=8 (1920x1080@60, I think that is only for default or menu)
- vsync_adjust=1 (I tried with 2 too, and it's ok)
- video_mode_ntsc=8
- video_mode_pal=9

All cores look perfect and go smooth except one, minimig.

The following image shows how there is a kind of vertical banding, you can see how whdload loading pattern and it does not show the perfect pixel.



It can be seen in lateral scroll games, such as turrican 2 or shadow of the beast. But specially in workbench it is as if there is a rescaling that does not look perfect pixel. What can be?

Thanks!

[Sorgelig]

It can be seen in lateral scroll games, such as turrican 2 or shadow of the beast. But especially in workbench it is as if there is a rescaling that does not look perfect pixel. What can be?

if you want to avoid any scaling, then you must use VGA output with monitor supporting Amiga resolutions.

[pedranic]

I already do that. I have CRTs for it, but I am trying to get the best output with HDMI (1920x1080) like other cores in Mister (SNES, MEGADRIVE).
Minimig is the only one that it has this "vertical banding", for that reason I thought it was a bad configuration issue.
Thanks!

[Sorgelig]

You may choose a better scaling filter like Lanczos 2 or 3.

[pedranic]

You may choose a better scaling filter like Lanczos 2 or 3.

I will try it when I get home with minimig. For other cores, Normal_Scanlines_30 filter work like a charm.

Thank you!

[kolla]

Is there a way to send cltr-a-a (or reset) to a running Mimimig core from the Linux side?

[R4MS]

Main_Mister does do this. It's not hard to find in the sources.

[Sorgelig]

key codes injection should work to simulate keyboard reset.

[kolla]

Yes, I found some generic code for simulating a keyboard from a shell console that does it.

(I sometimes have the issue that the Minimig core doesn't immediately boot, but needs an extra reset. I've sort of narrowed it down to "something about hard drive detection" with "newish" scsi.device, but nothing specific. This also happens with the MiST, btw)

[SegaMan]

Tried to play Banshee today (latest core).
Controls did not work.
Cant move around the plain.

Reconfig the controller settings did not work.
In other games i have no problems.

[retrofun]

(I sometimes have the issue that the Minimig core doesn't immediately boot, but needs an extra reset. I've sort of narrowed it down to "something about hard drive detection" with "newish" scsi.device, but nothing specific. This also happens with the MiST, btw)

Happened on MiST after loading a new minimig configuration.

Clearing the CPU Vector Table before resetting/starting the CPU fixes this for MiST.
https://github.com/retrofun/mist-firmwa ... 20419c7615

Maybe this also works for MISTer?!

[sonycman]

Hi!
I`am learning the Minimig verilog sources, and cannot figure out, how the slow memory configuration works.

In the menu we can set slow memory amount as: "none", "512K", "1M" and "1.5M".
In minimig_bankmapper.v register bank assigns as:

Code: Select all

bank[7:4] = { kick,kick256kmirror , chip3 | chip2 | chip1 | chip0,  kick1mb  | slow0 | slow1 | slow2 | cart} ;

So bit 4 goes for slow memory. But I cannot find in rest of the HDL code where this bit is used!

In minimig_sram_bridge.v accesses to slow memory just forwarded untouched to SDRAM (addresses in range 4-8 MB):

Code: Select all

assign address[22:18] = bank[6] ? 5'b111_11 : //access f8-fb and !ovl and !halt, map to fc-ff
                       (bank[7] ? {4'b111_1, address_in[18]} : //access to f8-ff or ovl 
                       (bank[5] ? {2'b0, bank[3]|bank[2], bank[3]|bank[1],address_in[18]} :
                        address_in[22:18]));

It seems for me that not matter how much of slow memory enabled in the menu - all of it enabled all the time.
Is this a bug, of just my misunderstanding?
Help me, please, figure out how the code is working, I'll be much appreciated!

Regards, Vlad.

[Sorgelig]

Memory to SDRAM mapping is done in TG68K.vhd.
Cannot tell more precise now as i'm busy by other cores.

[R4MS]

I guess, I've been the last to work on that code.

The memory layout is as follows:
Amiga - SD
0-$20 - 0 -$20
$A0-FF - $20-80

Bit 4 is used in this line in minimig_sram_bridge.v to initiate memory access

wire enable = |bank[7:0]; // indicates memory access cycle

The amount of Slow Ram is handled in gary.v:

assign sel_xram = ((t_sel_slow[0] & (memory_config[2] | memory_config[3]))
| (t_sel_slow[1] & memory_config[3])
| (t_sel_slow[2] & memory_config[2] & memory_config[3]));

and

assign sel_reg = cpu_address_in[23:21]==3'b110 ? ~(sel_xram | sel_rtc | sel_ide | sel_gayle) : 1'b0;

triggers access to the registers instead of memory on any access to the area from $c0-df, if it does not hit slow ram, or rtc, ide, gayle.

If you want to optimize the code, you could disable memory access in minimig_sram_bridge.v, when sel_reg|sel_rtc| sel_ide |sel_gayle | sel_cia

[sonycman]

Thanks for such a quick response!
Now I see. Its not about optimizing, just want to get how the thing work.

[sonycman]

But it seems i've succeeded to reduce amount of cycles in SDRAM controller, so it takes 4 less cycles than before. It allows to switch from 114MHz to 86MHz without touching the 28.6875MHz master clock.
In SysInfo the number is 12.70 instead of 12.93 which is not a big loss. 86MHz should give much more stability to the core. On 114MHz it suffers from instability and some builds are unstable.
It still needs more testing to make sure it works fine.

But by reducing the state machine you had violated memory timings:
tRC: 60ns min (~52ns in fact)
tRFC: 60ns min (~52ns in fact)

To correct tRFC second time slot must not access the memory and should go in IDLE state if the first slot activates REFRESH.

Just my 2 cents

[Sorgelig]

But by reducing the state machine you had violated memory timings:
tRC: 60ns min (~52ns in fact)
tRFC: 60ns min (~52ns in fact)

how you've counted it? RAS-RAS is 6 cycles. On 86MHz it's ~70ns.
Also tRC is for the same bank, so it's 12 cycles.

[sonycman]

My bad, I counted for the old clock 114 MHz, shame on me
For 86 MHz all seems fine.

Why the second slot only accesses non-zero banks?
tRC (same bank) after 6 86MHz clocks looking fine (69ns), there is no need for 12 clock delay, so it okay if first and second slots would access the same bank...

[Sorgelig]

Why the second slot only accesses non-zero banks?
tRC (same bank) after 6 86MHz clocks looking fine (69ns), there is no need for 12 clock delay, so it okay if first and second slots would access the same bank...

You can count amount of cycles to read 4 word burst. It's impossible to fit it into 6 cycles. Also don't forget auto-precharge time. So, only overlapped access with different banks can be accomplished here.

[petarku]

Hi guys ,
i am experiencing some slowdowns when i am playing sensible world of soccer whdload when there are a lot of players are on the pitch(after corners for example)
I am using latest minimig core.
Mister is connected to benq 702 using vga with composite_sync set to 1
configuration used is :
cpu 020
chipset : AGA
CHIP : 2M
FAST:25 M
SLOW : none


i was using already minimig in unAmiga clone and played swos without any slowdowns so think I am missing some here with configuration..
Any clues why there is slowdown ? Is there any video setting i need to change , except composite_sync everything else is on default ..
Thanks in advance ,
Petar

[Sorgelig]

Try Turbo: BOTH if not tried yet. You need to reboot the Amiga after change this option.

[petarku]

@Sorgelig that worked as a charm. Thank you very much !

[kolla]

When I create a 20GB disk image, name it for example test.dsk, and use HDToolBox of OS3.9 or 3.1.4, using an up-to-date scsi.device, and tell HDToolBox to "read Configuration", it comes out with way off values (0 cylinders, 11 heads, 63 blocks per track, 693 blocks per cylinder, which all add up to "1419264G (1386 Ter)" - same disk image used with emulated IDE controller under FS-UAE, with same scsi.device and same HDToolBox, works fine and shows sane values. So is this just me, or is something is wrong with the "IDE controller"?

[R4MS]

There are several problems with IDE... That's the next thing on my list, if everything works out I'll have some time soon. I've got the same issue with HDToolBox on 3.1.4.