I know, but no, that board has a Cyclone V SOC part. Same part as the one in the DE10-nano but in addition it has transceivers. It's a rather expensive board at $1.800: https://www.altera.com/products/boards_ ... v-soc.htmlSorgelig wrote:There are different Cyclone V chips. Some versions have no HPS like Cyclone V GX - and it almost doesn't produce the heat. Other versions like Cyclone V SE used in DE10-nano has HPS on-board - so it produces the heat due to this HPS (ARM CPU).ijor wrote:Actually, in one of the most expensive Altera dev boards, it mentions that a heatsink is normally not needed, except only on extreme conditions or when using engineering samples.
An idea ... It might be worth trying to enable both cores but use a lower CPU clock frequency, say, 600 MHz. You will probably get about the same performance as you have now with a single core at max speed, but power consumption (and then heat) would be significantly lower. Altera has a tool that let you estimate power with different CPU configurations.MiSTer Linux already uses a single core only. Another core is turned off ... i didn't explore the ability to change the CPU speed as ARM CPU in Cyclone lacks PM. Probably it's possible, but it will definitely will affect the performance. ARM side uses Linux ...
Ouch, has to be really a monster to take 85% in such big FPGA. Can you post a compilation report? What you mean it doesn't always succeed? It can't fit the design at all? It doesn't meet timing? Or what?For very big projects like ao486 occupying ~85% of FPGA it's not possible. ao486 is pretty extreme case, actually. I have to spend up to half day to compile it. Every compilation takes around 1h30m and not always successful.
For such huge projects the non free Quartus version makes a big difference. It has several compilation optimizations that are not available in the free edition. Unfortunately it is very expensive unless you have it at work or a special University license.
