MSX1 from Fabio Belavenuto for Mist and SiDi

[ManuFerHi]

This Fabio core has been ported by Yo_me to Mister, and ported to mist / SiDi by Rampa.
The SiDi version works without problem, but the Mist version I think only works with some versions of sdram.

VHD file - https://mega.nz/file/5oUw1KQZ#vjNHSkfoW ... crWQHFuM8M

Repo - https://github.com/RW-FPGA-devel-Team/MSX1FPGA_SiDi

I add the project for mist, in case someone who does not work wants to try different timings.

[Higgy]

Thanks. I will have to try it on my MiST but I expect it will not work.

Hopefully the fix which was applied to Sam Coupe, MSX2 and Archie Core for SDRAM timing can be applied to this Core.
My MiST had no issues once the timing changes was integrated into those other Cores. Probably a couple of years ago now the timing fix was found.

[rondc]

ManuFerHI ! Hello !!!

My MISTica has the same RAM than classic MiSTs and may be what you said about the speed of the RAM.
I have been trying to synthesize several approaches and there was not success, still not working.

Maybe Gyurco could do a couple of tries since he has a lot of experience with MIST RAMs.

[DanyPPC]

Many thanks, I will try it on my MiST/MiSTICA

[DanyPPC]

It doesn't work on MiSTica.

On MiST it stops on "Booting..."

[vebxenon]

Tested on real MiST. It gets stuck on "Booting..." screen.

[rondc]

@slingshot:

I have been yesterday making a lot of tests, in order to find the right clocks to make sdram to work.

I tried it with 0 degrees, -10, -15, -25, -30, and -90, when by default it was -45. None of the possible combinations has worked for me.
Then I tried to change the clocks, ck0 to 21.477273, ck1 at 85.909091 and ck2 just like ck1. I have not been lucky either, it keeps getting stuck in the boot.

Please, slingshot, Could you take a look to see if there is any chance it will work?. Thanks in advance.

[slingshot]

ManuFerHI ! Hello !!!

My MISTica has the same RAM than classic MiSTs and may be what you said about the speed of the RAM.
I have been trying to synthesize several approaches and there was not success, still not working.

Maybe Gyurco could do a couple of tries since he has a lot of experience with MIST RAMs.

The SDRAM doesn't have any speciality, just you have to program it correctly. Best to allow packing the IO regs into Fast Input/Output. That might sound scary, but only means that avoid combinatorial logic on the SDRAM in/output pins, and use only one target register for them. E.g. instead of:

Code: Select all

	if (a) out_a <= SDRAM_DQ else out_b <= SDRAM_DQ;

write

Code: Select all

	sdram_in <= SDRAM_DQ;
	if(a) out_a <= sdram_in; else out_b <= sdram_in;

Also set the constraints in the SDC well.
There are a lot of examples in other cores, I won't work on this one.

[rondc]

Thanks slinghot !
Let's see what we can do.

Where can we find some SDC documentation in order to learn how to configure ?.

Regards.

[slingshot]

Thanks slinghot !
Let's see what we can do.

Where can we find some SDC documentation in order to learn how to configure ?.

Regards.

Quartus handbook maybe. The input/output part of the .sdc is very unintuitive, just copy-paste the SDRAM part from another recent core (use the correct clock).

[ManuFerHi]

From the feedback I receive it works on all FPGAs that carry Alliance memory sdram, and it fails on Micron memories, SiDi as they all carry Alliance works in all, Mistica works in all those that carry the Alliance brand and original Mist only works with some Hynix memories.

[rondc]

Something similar happened with the SNES core when it started to be tested, in the end it was able to work on MIST and MiSTica with different RAM manufacturers.

The big problem I see with this core is that without the help and advice of someone who knows how to solve this kind of problems, it will make us have to learn and try until it works, if we succeed, of course.

There is not much more to comment, apart from saying that this core in SiDi works like a charm. If anyone is encouraged to try to make it work on the MiST with Micron, we will be very grateful.

[slingshot]

C'mon, it's an MSX1, the SDRAM bandwith requirements are nowhere near to the SNES. The SDRAM controller in SNES uses a 3-way bank interleaving, and runs at 126MHz. The MSX1's SDRAM controller should work even at 32MHz, but if it runs above 64MHz, then there is something very inefficiently implemented.
Hint: look at the Colecovision core, same CPU, same VDP.

[rondc]

OK !

Here is the core running with MiST and MiSTica with Micron RAM.
Please, test and feedback, seems to work fine.

Thanks a million to @rampa069, brilliant !

MSX1_MiST_Micron.rbf.zip

Enjoy. Cheers

[DanyPPC]

Thanks rondc, now it works on my MiST.

[rondc]

Here are latests updates:

Multiwrite enabled SDHC bigger than 2GB
Floppy Disk Mount

For MiST, MiSTica

MSX1_Mist_200808.rbf.zip

For SiDi

MSX1_Sidi_200808.rbf.zip

NEXTOR.SYS at vhd/sd root directory.

NEXTOR.SYS.zip

NEXTOR.ROM at msx1fpga directory.

NEXTOR.ROM.zip

Feedback Please.Cheers

[DanyPPC]

Thanks rondc, it works very well on my MiST

[DanyPPC]

Interesting the new MSX1 core for MiSTer.
It has a gui which permits to load a rom, select a mapper, insert a CAS or DSK (enable the fdd controller), etc...