Work on the Minimig core?

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apolkosnik
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Re: Work on the Minimig core?

Post by apolkosnik »

tobiflex wrote:I have implement my first try of the CHK2 and CMP2 Instructions here: https://github.com/TobiFlex/TG68K.C

But I need help here. Do these instructions do what they should? Who can write examples or test code?
cputester stop with false N- or V- Flag. But this is undefined behavior.
@tobiflex, you can use ccrmask as the last param to ignore the Flags.
e.g. cputest all abcd.b ccrmask or
cputest all abcd.b continue ccrmask

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Re: Work on the Minimig core?

Post by slingshot »

@tobiflex I've looked at the timing analysis of the tg68k, and there's a very long combinatorial path in the barrel shifter: the one which involves a hardware divider (inferred by the rem operator). This can fail even at 28MHz. I think it would be wise either to get rid of it somehow (if possible) or pipeline that long calculation into more cycles.

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Re: Work on the Minimig core?

Post by MasterOfGizmo »

slingshot wrote:I think it would be wise either to get rid of it somehow (if possible) or pipeline that long calculation into more cycles.
Uh ... for a second I was afraid my old barrell shifter was still lurking in Tobis code. But he has his own barrell shifter.

I think you can simply disable it by option:
https://github.com/TobiFlex/TG68K.C/blo ... l.vhd#L101

Anyway, pipelineing it basically means to return to a regular shifter. Perhaps something in-between makes sense. In the end a higher clocked core with a multi stage shifter might still shift faster than a lower clocked one with a single stage barrell shifter.
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Re: Work on the Minimig core?

Post by slingshot »

MasterOfGizmo wrote:
Anyway, pipelineing it basically means to return to a regular shifter. Perhaps something in-between makes sense. In the end a higher clocked core with a multi stage shifter might still shift faster than a lower clocked one with a single stage barrell shifter.
I just think about split to two phases - the whole calculation is ~36ns, it's more than the 28MHz system clock period!
But 1/4 of this is the inferred divider - if it can be spared, then it'll be good enough.
Or just split into two phases, that won't reduce the speed considerably, I think.

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Re: Work on the Minimig core?

Post by MasterOfGizmo »

There is an inferred divider? What does the shifter need a divider for?
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Re: Work on the Minimig core?

Post by slingshot »

MasterOfGizmo wrote:There is an inferred divider? What does the shifter need a divider for?
Not sure, but I think calculating the effective shift count based on the operand size and the given shift count:
https://github.com/TobiFlex/TG68K.C/blo ... U.vhd#L841

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Re: Work on the Minimig core?

Post by tobiflex »

slingshot wrote:@tobiflex I've looked at the timing analysis of the tg68k, and there's a very long combinatorial path in the barrel shifter: the one which involves a hardware divider (inferred by the rem operator). This can fail even at 28MHz. I think it would be wise either to get rid of it somehow (if possible) or pipeline that long calculation into more cycles.
OK, I hope I can find a way

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Re: Work on the Minimig core?

Post by slingshot »

tobiflex wrote: OK, I hope I can find a way
Great, thank you!

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Re: Work on the Minimig core?

Post by fpgaarcade »

tobiflex wrote:I have implement my first try of the CHK2 and CMP2 Instructions here: https://github.com/TobiFlex/TG68K.C

But I need help here. Do these instructions do what they should? Who can write examples or test code?
cputester stop with false N- or V- Flag. But this is undefined behavior.
I haven't had time to get my tests up and running yet.
Attached is my slightly modified itest to run in the sim. It tests the additional 020 instructions.
/MikeJ
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Re: Work on the Minimig core?

Post by retrofun »

Fix for the ILLEGAL.B cputest:
https://github.com/TobiFlex/TG68K.C/pull/4

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Re: Work on the Minimig core?

Post by sonycman »

Porting minimig on Xilinx currently, and Vivado reported many errors of type: declarations not allowed in unnamed block.
Someone has declared local registers under procedural blocks without names.
So I had to give names to such a blocks or move the registers outside of them.

Is the Quartus okay with it?

What was the meaning of declaring some local variables?

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Re: Work on the Minimig core?

Post by slingshot »

sonycman wrote:Porting minimig on Xilinx currently, and Vivado reported many errors of type: declarations not allowed in unnamed block.
Someone has declared local registers under procedural blocks without names.
So I had to give names to such a blocks or move the registers outside of them.

Is the Quartus okay with it?

What was the meaning of declaring some local variables?
You can name procedural blocks in Quartus, too. The meaning? Same as in any high-level language - those registers are used only in that block.
I can understand why the tool chokes on them - if you define two registers with the same name in two unnamed blocks, then you'll get a confusion in any netlist.

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Re: Work on the Minimig core?

Post by tobiflex »

fpgaarcade wrote:
tobiflex wrote:I have implement my first try of the CHK2 and CMP2 Instructions here: https://github.com/TobiFlex/TG68K.C

But I need help here. Do these instructions do what they should? Who can write examples or test code?
cputester stop with false N- or V- Flag. But this is undefined behavior.
I haven't had time to get my tests up and running yet.
Attached is my slightly modified itest to run in the sim. It tests the additional 020 instructions.
/MikeJ
Thank you Mike. Now I'll try to use it.

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Re: Work on the Minimig core?

Post by tobiflex »

retrofun wrote:Fix for the ILLEGAL.B cputest:
https://github.com/TobiFlex/TG68K.C/pull/4
Thank you, I took it over.

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Re: Work on the Minimig core?

Post by slingshot »

It's known that the IDE HDD's model name/serial number/etc. are looks like byte swapped (even in the Archie core, which uses the same IDE code as Minimig). But for some reason I found this in the firmware:
https://github.com/mist-devel/mist-firm ... hdd.c#L189
Basically byte swap is commented out - //not for 68000
Why not for 68000? Anyone knows that? I don't see issues with swapping with any CPU modes.

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Re: Work on the Minimig core?

Post by robinsonb5 »

slingshot wrote:It's known that the IDE HDD's model name/serial number/etc. are looks like byte swapped (even in the Archie core, which uses the same IDE code as Minimig). But for some reason I found this in the firmware:
https://github.com/mist-devel/mist-firm ... hdd.c#L189
Basically byte swap is commented out - //not for 68000
Why not for 68000? Anyone knows that? I don't see issues with swapping with any CPU modes.
Probably due to the heritage of the firmware code - which started out on little-endian ARM (for the original Minimig). I think it was Tobiflex who ported Minimig initially to a few platforms such as DE1 and Turbo Chameleon 64, which have no onboard ARM, and these have to use a second CPU within the core instead. He used a second TG68 to replace the ARM, so the firmware was now running on a big-endian CPU. (I believe Christian Vogelgsang was involved in that porting.) I made some changes to the TG68 version of the firmware which got backported to ARM, and also to OpenRisc (when Rok did some further work on the DE1 core), and I think that's the version that ultimately became the MIST firmware. The "not for 68000" comments were, I believe, from the original port from ARM to 68k.

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Re: Work on the Minimig core?

Post by slingshot »

Interesting history, the firmware run on the same CPU core as the Minimig itself?
But currently there shouldn't be an issue to do the byteswap then.

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Re: Work on the Minimig core?

Post by robinsonb5 »

slingshot wrote:Interesting history, the firmware run on the same CPU core as the Minimig itself?
But currently there shouldn't be an issue to do the byteswap then.
A second instance of the same CPU, yes.
At a quick glance, I believe the Identify Device response is a 16-bit-word-oriented buffer, but which has text portions within it. Since it's sent to the FPGA low-byte followed by high-byte the behaviour for the text portions is different between big- and little-endian CPUS, so on little-endian ARM the text part of the buffer should indeed by byte-swapped before sending.

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Re: Work on the Minimig core?

Post by slingshot »

Actually it doesn't depend on the receiving CPU, but there's an oddity in the ATA spec itself:
Although most multi-byte fields in ATA are little-endian, some fields are unusual:
a) The IDENTIFY (PACKET) DEVICE data SERIALNUMBER field, MODELNUMBER field, and FIRMWAREREVISION field, and possibly the MEDIASERIALNUMBER field each contain ASCII characters representing an ASCII string. However, they do not contain the characters in normal string order (with the first character at byte 0, the second character at byte 1, etc.). For historical reasons, each pair of bytes is swapped (byte 0 with byte 1, byte 2 with byte 3, byte 4 with byte 5, etc.).

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Re: Work on the Minimig core?

Post by robinsonb5 »

slingshot wrote:Actually it doesn't depend on the receiving CPU, but there's an oddity in the ATA spec itself:
Although most multi-byte fields in ATA are little-endian, some fields are unusual:
a) The IDENTIFY (PACKET) DEVICE data SERIALNUMBER field, MODELNUMBER field, and FIRMWAREREVISION field, and possibly the MEDIASERIALNUMBER field each contain ASCII characters representing an ASCII string. However, they do not contain the characters in normal string order (with the first character at byte 0, the second character at byte 1, etc.). For historical reasons, each pair of bytes is swapped (byte 0 with byte 1, byte 2 with byte 3, byte 4 with byte 5, etc.).
Yes, that's right - but we're not talking about the receiving CPU here - we're the sender!
That swapping happens automatically on a big-endian CPU (when the firmware's running on 68k) because the buffer's sent in 16-bit words, first the low byte then the high byte - so the text string "ABCD" is sent 'B', 'A', 'D', 'C'.
On a little-endian CPU (such as the MIST's onboard ARM) the same buffer is sent 'A', 'B', 'C', 'D', so needs to be byte-swapped.

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Re: Work on the Minimig core?

Post by slingshot »

Ah, ok, agreed.
Just first I assumed the commented out byteswap function is because of the receiver 68000, not what the firmware runs on.

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Re: Work on the Minimig core?

Post by robinsonb5 »

slingshot wrote:Just first I assumed the commented out byteswap function is because of the receiver 68000, not what the firmware runs on.
Yes, indeed - I'd have assumed the same if I'd not known about the firmware previously running on 68k.

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Re: Work on the Minimig core?

Post by sonycman »

Hello.
I want to simulate the CPU cache, integrated in memory controller (file cpu_cache_new.v).

I far as i understand, by default it is disabled, so i need to enable it by setting right bits via cpu_cache_ctrl signal?
This signal is connected directly to CACR CPU output, so this could be done only in code running on it.

Am i right?

Could the cache be activated with 68000 cpu mode, or it must be 68020 only?

Thanks in advance!

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Re: Work on the Minimig core?

Post by uchristo »

Is there some kind of interrim-Build available for all those who didn't set up the whole Buildsetup?

I'd like to test if the several Math-fixes will have effect on WHDLoad-Version of Rainbow Islands (crashes on MiST MiniMigAGA, works on UAE/Real Hardware)

WHDLoad Dump included
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Re: Work on the Minimig core?

Post by jokker »

Here's is one I did recently that seems to work on my MIST.

I noticed that Gods worked for me in WHDLoad now when before it didn't so there has definitely been some improvements. My thanks for the hardwork by everyone.
uchristo wrote:Is there some kind of interrim-Build available for all those who didn't set up the whole Buildsetup?

I'd like to test if the several Math-fixes will have effect on WHDLoad-Version of Rainbow Islands (crashes on MiST MiniMigAGA, works on UAE/Real Hardware)

WHDLoad Dump included
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