Mister SNES port to MIST possible?

[ijor]

For example, I changed the clk_sdram pin in SiDi for another. Now the SNES core doesn't work for me at any phase. The only way to make it work has been in phase 0 and with the option in PLL Zero delay mode. Now it is very stable.

I'm not sure using Zero delay is a good idea in this case. Zero Delay is probably not what you think. You are applying a shift blindly and without knowing. Furthermore, you are adding an unnecessary clock latency and jitter.

... The only way to make it work has been in phase 0 and with the option in PLL Zero delay mode. Now it is very stable.

Just check if the pin used is a dedicated output of a PLL. Using the dedicated output greatly reduces clock delay. However if the SDRAM doesn't require any phase shift @126 MHz, then it's really fast and connected with 0 clock skew.

No. Enabling Zero Delay Buffer mode does produce a shift. As a matter of fact you always have some kind of shift, implicitly or explicitly.

All those compensation modes compensate between the input to the PLL and one of the outputs of the PLL (something that you don't care here at all unless you cascade PLLs). They don't compensate between different PLL outputs.

[slingshot]

No. Enabling Zero Delay Buffer mode does produce a shift. As a matter of fact you always have some kind of shift, implicitly or explicitly.

All those compensation modes compensate between the input to the PLL and one of the outputs of the PLL (something that you don't care here at all unless you cascade PLLs). They don't compensate between different PLL outputs.

True, I just got the conclusion of the very small clock skew because it worked with a 0 phase shift @126 MHz, not because of the zero delay mode (but that deduction could be wrong, too). AFAIK the skew created by the zero delay mode affects all off the clock networks. And yes, aligning the output phase to the input phase is quite useless (that's why I prefer to use the PLL which has a dedicated output pin to SDRAM_CLK, and not the one which has a dedicated input from the main crystal).

[ijor]

AFAIK the skew created by the zero delay mode affects all off the clock networks.

Aligning and compensating are two different things. All internal clocks are aligned, unless explicitly shifted, and don't require compensation. But the external output is not aligned with the internal ones and might have a significant skew even with no phase shift.

And yes, aligning the output phase to the input phase is quite useless (that's why I prefer to use the PLL which has a dedicated output pin to SDRAM_CLK, and not the one which has a dedicated input from the main crystal).

The delay produced by not using a PLL dedicated output is a non-issue if you shift. The additional jitter is more important because at the higher frequencies it will be more difficult to meet timing. But Altera/Intel don't consider this critical. Newer versions of Quartus don't issue the warning anymore.

[Televicious]

I just wanna say, I kicked my bro's butt in killer instinct this xmas all thanks to your hard work. Very very satisfying. Perfect recreation.

[slingshot]

I just wanna say, I kicked my bro's butt in killer instinct this xmas all thanks to your hard work. Very very satisfying. Perfect recreation.