Mister SNES port to MIST possible?

[lips2k15]

I have seen that the SNES core for the Mister seems to be comming along quite nicely - has anybody attempted to port it to MIST or is the MIST not powerful enough? I would be nice to have both the Megadrive and SNES on the MIST!

[Gehstock]

Nope Sorry

[lips2k15]

How come? What are the difficulties? It can do the megadrive and amiga and both are pretty tricky so whats so different bout the snes?

[slingshot]

Last time I checked the original sources, it was written in a way that consumes too much FPGA resources. The CPU is about 10k LCs, the PPU is 14k (just to compare: the Genesis VDP consumes 3700 LCs, the PC-Engine about 5000). So just these two components would fill the FPGA, no sound, no MiST toplevel, nothing else.

[jotego]

The CPU is about 10k LCs

It would take less room to use a small CPU running at high speed to emulate the SNES CPU at cycle accuracy. That’d be a way to make this fit.

[slingshot]

The CPU is about 10k LCs

It would take less room to use a small CPU running at high speed to emulate the SNES CPU at cycle accuracy. That’d be a way to make this fit.

As I've read articles such "Why an i7 is needed for cycle-perfect SNES emulation", and so, I wonder what kind of CPU on the FPGA could allow SNES emulation. And if it found, then we're back to software emulators. Btw, I think the CPU of this size is acceptable (not much more than the Genesis M68000+Z80), but 4 times bigger PPU than VDP probably could be optimised. And after that, there's still the sound DSP, which is also huge.

[jotego]

As I've read articles such "Why an i7 is needed for cycle-perfect SNES emulation", and so, I wonder what kind of CPU on the FPGA could allow SNES emulation. And if it found, then we're back to software emulators. Btw, I think the CPU of this size is acceptable (not much more than the Genesis M68000+Z80), but 4 times bigger PPU than VDP probably could be optimised. And after that, there's still the sound DSP, which is also huge.

I meant only the CPU, not the whole system. A moderate speed CPU (30~50 MHz) should be able to emulate at full speed this other CPU. But if the current CPU size is not that bad, then let's look at the other elements.

[Sorgelig]

it's called microcode CPU.
By the way, there is MCL65 CPU which is written in microcode. 65c816 is evolution of 6502.
But base SNES has 2 CPUs. Another one is SPC700 in APU.

[Sorgelig]

Besides the LE, SNES has a lot of RAM. 256KB on SNES itself and up to 64KB(BSRAM) on cart.
If don't emulate the accelerators, then it's possible to move WRAM(128KB) and BSRAM(64KB) to SDRAM as they aren't accessed at the same time.
There is still ARAM(64KB) which is accessed from SPC700 and VRAM(64KB) accessed by PPU.
Probably with some caching, it will be possible to fit it to SDRAM too.
SNES is very sensitive to cycle accuracy (unlike Genesis). So either it's accurate or many games won't work. Genesis uses wait signal from SDRAM in order to work. SNES won't work correct with wait. So, RAM controller must prepare the data on-time.

[Gehstock]

The pgate1 Implementation looks more interesting except for Memory

https://pgate1.at-ninja.jp/SNES_on_FPGA/rpt_DE2-115.htm

Too bad that there is no code

[Sorgelig]

The pgate1 Implementation looks more interesting except for Memory

do you know compatibility level of pgate1?

[Gehstock]

No but According by his Pictures that shuld be very good (for the pure SNES)

unimplemented And something like that excuse
· Graphic
　　interlacing: The game you are using is very rare. Also, because it outputs with VGA, it does not match timing.
　　Rectangular sprite: out of spec. Also I can not find the scene being used.
　　Mosaic of Mode 7: Sobori.
Sound
　　Gaussian interpolation: Because of excessive muffling, frequency adaptive linear interpolation is substituted.
　　APU speed variable: It seems unnecessary for now.
· Other
　　PAL mode: Currently only supports NTSC mode.

[tatouine]

The pgate1 Implementation looks more interesting except for Memory

https://pgate1.at-ninja.jp/SNES_on_FPGA/rpt_DE2-115.htm

Too bad that there is no code

There's a Mister WIP version for compilation (bottom page):

https://pgate1.at-ninja.jp/SNES_on_FPGA/

[Gehstock]

This is only for FPGA Configuration no Code

[ReedSolomon]

This is only for FPGA Configuration no Code

Well there is now

[Gehstock]

Code must be Converted (Quartus will not support SFLP)

[slingshot]

The biggest challenge of the MiSTer core is not the size (maybe cutting the extra chips, moving CPU microcode to BRAM, and it could fit), but the memory bandwidth of that single SDRAM chip. Lot of components have to access it simultaneously, and SNES is more sensitive to delays (it won't wait for RAM, or if you make it to wait, then games will crash).

[slingshot]

Well guys, maybe MiST is old. MiST is outdated. MiST is obsolete. Already a retro device. And there are very few developers.
...but still good to play some Super Mario Kart:
https://github.com/gyurco/SNES_MiSTer/r ... /tag/test1

[vebxenon]

Well guys, maybe MiST is old. MiST is outdated. MiST is obsolete. Already a retro device. And there are very few developers.
...but still good to play some Super Mario Kart:
https://github.com/gyurco/SNES_MiSTer/r ... /tag/test1

I'm going to test it right now.

[Gehstock]

Wow great Work

[vebxenon]

I've tested Street Fighter II, Super Mario Kart and Final Fight. That's outstanding! . I'm really impressed. Thanks very very much!

I've put some screenshots here:

https://twitter.com/veb_xenon/status/11 ... 20768?s=19

[sebdel]

Well guys, maybe MiST is old. MiST is outdated. MiST is obsolete. Already a retro device. And there are very few developers.
...but still good to play some Super Mario Kart:
https://github.com/gyurco/SNES_MiSTer/r ... /tag/test1

That's unbelievable. Is there something you can't do ?

[squid4]

What witchcraft is this? What we thought was impossible, slingshot strikes again keeping the MiST alive! Outstanding work!

[slingshot]

For the record, 95% of the credits should go to srg320 for his outstanding work on all the custom chips in SNES.

And who wants to hear some technical details about the MiST port: recently I've experimented with SDRAM bank interleaving techniques. As the SDRAM chip is divided to 4 banks internally, and these are more or less accessible independently, it was possible to split the SDRAM controller to 3 almost independent ports. This allowed to have the CPU's ROM, work RAM, BSRAM, the SPC and SDSP's RAM and SPPU's VRAM all in the SDRAM. It still has to be run in very high frequency (at 128MHz), and can have occasional glitch in VRAM access, but the result is adequate I think. As SNES is basically a 8-bit machine, it does a lot of 8 bit accesses to its RAMs, which is also not very ideal for the 16-bit wide SDRAM.

[NegSol]

Great news! Cheers I will test it soon