NEW OR UPDATED ARCADE CORES

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Re: NEW OR UPDATED ARCADE CORES

Post by vebxenon »

Jotego has released the beta of Double Dragon:

https://twitter.com/topapate/status/1208312526565527554

So (hope) soon a public release will see the light :cheers: :cheers:
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Re: NEW OR UPDATED ARCADE CORES

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Re: NEW OR UPDATED ARCADE CORES

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Just a computer and videogame lover :)

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Re: NEW OR UPDATED ARCADE CORES

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retrofun wrote:F1 Dream by Jotego:

https://github.com/jotego/jtbin/tree/master/mist
That's outstanding :D
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Re: NEW OR UPDATED ARCADE CORES

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Just a computer and videogame lover :)

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Re: NEW OR UPDATED ARCADE CORES

Post by Darfpga »

Popeye arcade VHDL source code for DE10_lite is available here :

https://sourceforge.net/projects/darfpg ... re%20VHDL/

Video 15kHz and 31kHz mode : OK (interlaced for 15kHz)
Sound : OK
Cocktail mode : NO

Feel free to port to MiST/MiSTer (or use Jotego's core). Bring your own roms.
(roms come from both popeye.zip and popeyeu.zip - see make_prom.bat)

Note : this is not a port of Jotego's core. I discover its core too late to give up with my own core.

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Re: NEW OR UPDATED ARCADE CORES

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Darfpga wrote:Popeye arcade VHDL source code for DE10_lite is available here :

https://sourceforge.net/projects/darfpg ... re%20VHDL/

Note : this is not a port of Jotego's core. I discover its core too late to give up with my own core.
Too bad it's already done. But except this, all of your cores are working on MiST ;)
Just question about a line in CTC counter:
https://github.com/Gehstock/Mist_FPGA/b ... r.vhd#L135
Why should the other periods other than the first halved? It breaks one game (Kozmik Kroozr), and not sure if it helps in others (didn't try all).

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Re: NEW OR UPDATED ARCADE CORES

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slingshot wrote: Too bad it's already done.
Right. Anyway doing this game was interessting for me.
slingshot wrote: But except this, all of your cores are working on MiST ;)
Fine, Thanks.
slingshot wrote:
Just question about a line in CTC counter:
https://github.com/Gehstock/Mist_FPGA/b ... r.vhd#L135
Why should the other periods other than the first halved? It breaks one game (Kozmik Kroozr), and not sure if it helps in others (didn't try all).
Don't understand the term 'first period other than the first'. Every period are halved the same.

Halving period is unecessary from the CTC datasheet (that's why there is a comment at end of line) but halving period is there since the very first game I do (Kick/Kickman). As far as I can remind me I have to half period since the game was too slow. At that time I just thought it was due to the fact that my core is progessive instead of interlaced. Anyway I carefully seek CTC datasheet and game schematic to find out a clock divider mistake but never found a good explanation. I do fine comparision with MAME debug of scanline counter when interrupts occurs. But MAME is not always a good reference. The best comparison should be a real hardware but I don't have one. Another explanation may come from the interlaced to progressive conversion that could bring some artefacts. You can find some explanation for interrupts mechanism at the beginning of VHDL code kick.vhd.

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Re: NEW OR UPDATED ARCADE CORES

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Darfpga wrote: Don't understand the term 'first period other than the first'. Every period are halved the same.
First it set to the "normal" value:
prescale_in <= prescale_max; @line 86

Then after it expires, it's set to the half.
But if it fixes Kickman, then OK.

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Re: NEW OR UPDATED ARCADE CORES

Post by jotego »

Darfpga wrote:Popeye arcade VHDL source code for DE10_lite is available here :

https://sourceforge.net/projects/darfpg ... re%20VHDL/

Note : this is not a port of Jotego's core. I discover its core too late to give up with my own core.
It’s great there are two versions of Popeye then. Note that mine is already ported to MiSTer/MiST but the more the merrier. :-)
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Re: NEW OR UPDATED ARCADE CORES

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slingshot wrote: First it set to the "normal" value:
prescale_in <= prescale_max; @line 86

Then after it expires, it's set to the half.
But if it fixes Kickman, then OK.
Hum, yes you are right. I think that I forgot to set half value also for line 86. At the moment I can't remind precisely how the ctc is programmed. I think that this value is set only once at start up, so it should have no impact later during running time.

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Re: NEW OR UPDATED ARCADE CORES

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jotego wrote:
Darfpga wrote:Popeye arcade VHDL source code for DE10_lite is available here :

https://sourceforge.net/projects/darfpg ... re%20VHDL/

Note : this is not a port of Jotego's core. I discover its core too late to give up with my own core.
It’s great there are two versions of Popeye then. Note that mine is already ported to MiSTer/MiST but the more the merrier. :-)
Hi Jose, so we do the same game! I guess that yours is verilog as usual and mine is vdhl as usual. I think that I am going to have a look at your code, although I'm not very familiar with verilog, but this game was a little tricky and unusual at the sprite machine level. I wonder how you do this part.

Big respect to you and your great work since GnG. Some day I certainly try to port it to my board. Thanks for sharing.

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Re: NEW OR UPDATED ARCADE CORES

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Darfpga wrote: Hum, yes you are right. I think that I forgot to set half value also for line 86. At the moment I can't remind precisely how the ctc is programmed. I think that this value is set only once at start up, so it should have no impact later during running time.
The programmed value usually stays the same, and every (re)start of the timer will do one full cycle, and (if not stopped) will do half-cycles after that. But not much visible effect, except in Kosmik Kroozr (when it introduces a crash - normal second cycle will fix it). Probably the CPU stops the timer after the first period expire, and restarts it after a while - the halving is not in effect in this case.

Meanwhile updated you Traverse USA core, included a Shot Rider mode (flip, sprite gfx addressing and palette addressing is affected):
https://github.com/gyurco/Mist_FPGA/com ... db6ac89f29

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Re: NEW OR UPDATED ARCADE CORES

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slingshot wrote: Meanwhile updated you Traverse USA core, included a Shot Rider mode (flip, sprite gfx addressing and palette addressing is affected):
https://github.com/gyurco/Mist_FPGA/com ... db6ac89f29
Fine, good job.

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Re: NEW OR UPDATED ARCADE CORES

Post by jotego »

Darfpga wrote: Hi Jose, so we do the same game! I guess that yours is verilog as usual and mine is vdhl as usual. I think that I am going to have a look at your code, although I'm not very familiar with verilog, but this game was a little tricky and unusual at the sprite machine level. I wonder how you do this part.

Big respect to you and your great work since GnG. Some day I certainly try to port it to my board. Thanks for sharing.
I was planning to look at yours too!

I never got the protection to work. I have to use unprotected ROMs. I have all the logic working as with the original architecture, which as you know is quite obscure and unusual. I think the graphics can be reworked to avoid interlacing without affecting fidelity to timing or anything noticeable by the user. I don't think I will go as far as to do that, though as I have other things in my basket right now.

Another nasty thing is the video pixel frequency. That 20.16 MHz is not a fraction of either 27MHz (MiST) or 50MHz (MiSTer), at least not in a single PLL step. So I am running it at 20MHz, which means 0.8% slower video. I know it is a small difference but we are here for accuracy, aren't we? Using a fractional clock divider to achieve 20.16MHz doesn't produce a stable analogue video signal so that's not an option.
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Re: NEW OR UPDATED ARCADE CORES

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jotego wrote: I never got the protection to work. I have to use unprotected ROMs.
I've just added protection algorithm. Seem's to be OK at least for level 1 (never reach more atm :-) )
jotego wrote: I have all the logic working as with the original architecture, which as you know is quite obscure and unusual.
I still keep the architecture as near as possible to the original one. Sprite DMA mechanism is kept identical, only not using Z80 the bus request/grant. Indeed it takes me a good amount of times to understand that part because of no documentation for PAL 3E and 4E.

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Re: NEW OR UPDATED ARCADE CORES

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Darfpga wrote: Hum, yes you are right. I think that I forgot to set half value also for line 86. At the moment I can't remind precisely how the ctc is programmed. I think that this value is set only once at start up, so it should have no impact later during running time.
Now reading the CTC datasheet, and I think the counting has an off-by-one error: it should not expire when it is 0, but when the next value will be zero (many other timer implementation works this way if I remember correctly - M68901 and the MOS CIA, too). Setting to 0 will mean 256 steps then. As there are still two crashing/freezing games (Power Drive and Journey), need to debug more...
Upd.: I see the 0 case is handled by a 8th bit in the counter. So the crashing is because of something else. But still can cause slowdown: setting the counter to 1 will wait for 2 prescaler cycles instead of 1.

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Re: NEW OR UPDATED ARCADE CORES

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slingshot wrote:
Darfpga wrote: Hum, yes you are right. I think that I forgot to set half value also for line 86. At the moment I can't remind precisely how the ctc is programmed. I think that this value is set only once at start up, so it should have no impact later during running time.
Now reading the CTC datasheet, and I think the counting has an off-by-one error: it should not expire when it is 0, but when the next value will be zero (many other timer implementation works this way if I remember correctly - M68901 and the MOS CIA, too). Setting to 0 will mean 256 steps then. As there are still two crashing/freezing games (Power Drive and Journey), need to debug more...
Upd.: I see the 0 case is handled by a 8th bit in the counter. So the crashing is because of something else. But still can cause slowdown: setting the counter to 1 will wait for 2 prescaler cycles instead of 1.
Each mcr game may use interrupt in its own manner. I already saw difference between kick and others. I first encounter problems with how the CPU catch interrupt vector rather than count accuracy. For kick I remember that there are interrupt linked to the scanline and others that just are free counter. I don't think that the count need to be very very precise. Does the crash or freeze arise rapidly ?

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Re: NEW OR UPDATED ARCADE CORES

Post by slingshot »

Darfpga wrote:
Each mcr game may use interrupt in its own manner. I already saw difference between kick and others. I first encounter problems with how the CPU catch interrupt vector rather than count accuracy. For kick I remember that there are interrupt linked to the scanline and others that just are free counter. I don't think that the count need to be very very precise. Does the crash or freeze arise rapidly ?
In Kozmik Kroozr, it was totally random, until I returned to normal prescaler setting.
In Journey, crashing is always at the same point <- still need to debug.

I start to wonder if the frame interrupt is not twice as fast as it should be - line493 should be reached once/full frame (30 Hz rate). Now it's fired in every frame in progressive mode and every half-frame in interlace (60 Hz). Journey just crashes drawing the top half of the screen. Usually the vertical counter should count odd numbers in odd frames, even number in even frames.

Upd.: Well, turned out the problem was more complex:
- frame interrupt rate should be 30Hz
- the counter issues already mentioned
- the interrupt ack is a bit more complex: while the CPU INTACK cycle clears the interrupt, it'll still prevent the same and lower level interrupts until a RETI instruction is detected on the bus. Solved by adding "in-service" bits to all levels.

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Re: NEW OR UPDATED ARCADE CORES

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slingshot wrote: I start to wonder if the frame interrupt is not twice as fast as it should be - line493 should be reached once/full frame (30 Hz rate). Now it's fired in every frame in progressive mode and every half-frame in interlace (60 Hz). Journey just crashes drawing the top half of the screen. Usually the vertical counter should count odd numbers in odd frames, even number in even frames.
I've written many explanation about that in kick.vhd. For sure it may be different for Journey or any other game. I'm going to check how it works for Journey.

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Re: NEW OR UPDATED ARCADE CORES

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Darfpga wrote: I've written many explanation about that in kick.vhd. For sure it may be different for Journey or any other game. I'm going to check how it works for Journey.
Yeah, I found it:
ONly channel 3 is trigered by hardware signal line 493.
I think it's rate should be 30 Hz in other games, too - how can it reach line 493 in every half picture? (easily solved by adding top_frame='1' condition).
I've already fixed Journey (explanations above). I'll clean up the code and upload in the weekend.

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Re: NEW OR UPDATED ARCADE CORES

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slingshot wrote: I think it's rate should be 30 Hz in other games, too - how can it reach line 493 in every half picture? (easily solved by adding top_frame='1' condition).
I've already fixed Journey (explanations above). I'll clean up the code and upload in the weekend.
Yeah, good job. Maybe it will fix the unattended 'wait for credits' that occurs in theses games. I will give it a try as soon as you upload.

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Re: NEW OR UPDATED ARCADE CORES

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Thank you both for improving arcade cores! :cheers:

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Re: NEW OR UPDATED ARCADE CORES

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Darfpga wrote:
slingshot wrote: I think it's rate should be 30 Hz in other games, too - how can it reach line 493 in every half picture? (easily solved by adding top_frame='1' condition).
I've already fixed Journey (explanations above). I'll clean up the code and upload in the weekend.
Yeah, good job. Maybe it will fix the unattended 'wait for credits' that occurs in theses games. I will give it a try as soon as you upload.
Uploaded there:
https://github.com/gyurco/Mist_FPGA/tre ... y_MiST/rtl
I've added a z80ctc_top to keep the arcade board cleaner, and to encapsulate the RETI detector.
Now only Power Drive doesn't work.

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Re: NEW OR UPDATED ARCADE CORES

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slingshot wrote: I've added a z80ctc_top to keep the arcade board cleaner, and to encapsulate the RETI detector.
Now only Power Drive doesn't work.
I'm digging my mistake since the early Kick which I wrote for 31kHz/60Hz progressive mode :

- you are right about the prescale counter max value the divide by 2 is useless for interrupt 0 and 1 since the counter are reseted during service routine and restarted during interrupt 3 service routine. Interrupt 3 maybe affected since programmed with a value of 1 which could become 0 when divided by 2. Interrupt 2 may be affected since programmed only once at start-up and then not reseted nor reprogrammed. Anyway removing the wrong divide by 2 seems not to change the game behaviour.

- then, following the idea of a 30Hz rate for ctc_trg3 which launch interrupt 3, I set this trigger every other frame to get the expected 30Hz from the 60Hz VGA line scanner and I found the game to be much too slow (eg. it takes around 16s for the balloons to reach the top of the screen in attrack mode, instead of 8s with MAME). I check schematics and MAME machine/mcr.c everything leads to the value that you tell : 30Hz rate. I have no explanation about why the game is too slow with this rate.

I'm going to look at your RETI detector.

PS : Journey uses nearly the same ctc programming scheme except that the role of counter/interrupt 1 and 2 are swapped and the counter value are sligtly different with respect to Kick.

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