Genesis / Megadrive core ported to MiST

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jotego
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Re: Genesis / Megadrive core ported to MiST

Post by jotego »

mahen wrote:Something is really funny in Thunder Force IV : ingame music stalls until the player's ship fires. Then music seems to be playing at the shooting pace.
(I have no idea if what I say in understandable ;)
I have just tried the game. OMG it's the weirdest thing! If I was trying to make that on purpose, I would fail! :lol:

I'll look into it this week. I have also heard some clues in other games that may be pointing to crosstalk between operators: a control signal from one operator gets mixed in the pipeline with that of a different operator because phisically there is only one sound operator, but virtually there are 24 of them. So I need to be cycling the signals of each virtual operator through the real one. I may have a signal from one operator getting mixed with the signal of another.
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Re: Genesis / Megadrive core ported to MiST

Post by vebxenon »

This error with Thunder Force IV happened even in early emulators.

And yes, theres are some games with strange sounds and notes. But well... let's wait :)
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Re: Genesis / Megadrive core ported to MiST

Post by alexh »

I think it has something to do with VDP DMA VRAM FILL? Thunder Force IV makes extensive use of this. Software emulators had to improve their VRAM FILL accuracy for this game.

Perhaps if it is not emulated/recreated correctly the audio core gets no DMA access for a while and then lots of data very quickly? Where in the real hardware it is paced correctly?

A quick search of old (pre-2011) forum posts can find the technical details

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Re: Genesis / Megadrive core ported to MiST

Post by vebxenon »

New release https://github.com/jotego/jt12/tree/master/fpgagen :D , let's wait for the changelog :)
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Re: Genesis / Megadrive core ported to MiST

Post by jotego »

I have worked a lot the last two weeks in order to improve sound quality. I have added FIR filters and a better sigma-delta in order to have a proper signal processing chain at least on the digital side. I have not seen FIR filters for interpolation before the sigma-delta DAC in any other retro FPGA core so this was really cool to me. I worked on an improved PSG sound core (JT89) too. The whole thing was very exciting.

However, we have a complex implementation of the Genesis core inherited from a different project. I do not quite understand why but the problem is that we are having many, many difficulties when trying to put the blocks together. Timing issues everywhere. This is a similar problem to what I found when I tried to add JT51 to the Atari ST (MiST) core. If the base core is not robust in terms of timing, as more stuff is added to the FPGA the whole thing just breaks down. I know that JT12 itself is fine because I can test it independently. But putting it together with the rest of the system has shown to be impossible for the last week.

I am going to take some time off now. I have been spending many hours everyday on this for the last two months. I think I have delivered a good JT12 module. It is only missing the LFO at the moment, but that is something minor that I will eventually fix. The other issue, the sounds in Thunder Force IV, is probably related to the timing issues we have at FPGAgen system level and not JT12 itself. Other sound artifacts are related to the signal chain used and I have also fixed that as I said in the first paragraph.

I will go back to mundane things like dusting off the shelves of my house, which I have not done in the last two months :oops: . I hope the timing of FPGAgen gets fixed by the rest of team. robinsonb5 and phoboz are putting a lot of effort on this too. Or maybe someone new comes to the project and fixes timing... Eventually, with timing fixed I will come back to connect the latest JT12 incarnation to FPGAgen and we will have sound completed.

Sorry to keep you all waiting!
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Re: Genesis / Megadrive core ported to MiST

Post by vebxenon »

Thanks for your great job, Jotego!
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Re: Genesis / Megadrive core ported to MiST

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jotego wrote: However, we have a complex implementation of the Genesis core inherited from a different project. I do not quite understand why but the problem is that we are having many, many difficulties when trying to put the blocks together. Timing issues everywhere. This is a similar problem to what I found when I tried to add JT51 to the Atari ST (MiST) core. If the base core is not robust in terms of timing, as more stuff is added to the FPGA the whole thing just breaks down. I know that JT12 itself is fine because I can test it independently. But putting it together with the rest of the system has shown to be impossible for the last week.
Make sure there are no asynchronous design is used in any part of project. Check is there are warnings like "Found signal xxx used as a clock without declaration." - or something like this.
If project is really large then adding more info into .sdc file is unavoidable. I hope i will understand this file someday...

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Re: Genesis / Megadrive core ported to MiST

Post by jotego »

alexh wrote:I think it has something to do with VDP DMA VRAM FILL? Thunder Force IV makes extensive use of this. Software emulators had to improve their VRAM FILL accuracy for this game.

Perhaps if it is not emulated/recreated correctly the audio core gets no DMA access for a while and then lots of data very quickly? Where in the real hardware it is paced correctly?

A quick search of old (pre-2011) forum posts can find the technical details
I don't know about the VDP. I have checked what is special about TFIV in terms of YM2612 and it is the only game I have seen that uses the two internal timers of YM2612 (actually the rest of the Thunder Force series does it too). This has to do to how the Z80 determines the rythm of the music. There are three options:

1. Some internal Z80 counter (most games, eg Sonic)
2. Use timer A or timer B from YM2612 to advance music when the timer flag is set (eg Ghouls'n Ghosts uses timer B)
3. Use both timers (Ultra Force series)

So I focused on the timers but I have not found issues in my implementation. That's why I think it has something to do with timing violations in the FPGA in the signal path from flag A/B to the CPU.
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Re: Genesis / Megadrive core ported to MiST

Post by alexh »

I have no experience with the Altera toolchain or I would offer to help. I'm strictly a Xilinx man

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Re: Genesis / Megadrive core ported to MiST

Post by ijor »

Some cores I've seen have problems with one clock being derived (one clock divided to produce a slower clock) and then having hold timing issues. You should be able to see the failing paths on the timing report. These cases are usually not too difficult to fix. Ideally remove the clock division and replace with a clock enable, or if possible use a PLL to perform the division. Otherwise some additional delay on the problematic paths might be needed. Quartus sometimes can do that automatically. But if not, it can be done manually.

If the problem is that the whole design is too close to the original implementation, it might have so many async issues that it would need some kind of major redesign.

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Re: Genesis / Megadrive core ported to MiST

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ijor wrote:Some cores I've seen have problems with one clock being derived (one clock divided to produce a slower clock) and then having hold timing issues. You should be able to see the failing paths on the timing report. These cases are usually not too difficult to fix. Ideally remove the clock division and replace with a clock enable, or if possible use a PLL to perform the division. Otherwise some additional delay on the problematic paths might be needed. Quartus sometimes can do that automatically. But if not, it can be done manually.
This is called "asynchronous design" where any random signal used as a clock. That's what i wrote above.
I think jotego should be already experienced to know about this. But sometimes original design comes from other authors and can include some flaws. I know Quartus not always reports about signals used as a clock not being declared as a clock. I think it depends on sdc file content. I remember i cleaned sdc file (i left only necessary records) which i used for almost all my cores, and Quartus started to report about such problems which compiled before without warnings.

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Re: Genesis / Megadrive core ported to MiST

Post by alexh »

Sorgelig wrote:This is called "asynchronous design" where any random signal used as a clock. That's what i wrote above.
I think ijor is talking about when you have two (or more) clocks in your design which are different frequencies but you can make them (rising) edge synchronous. In that situation you can define the fastest clock and use a clock enable to for the slower clocks (instead of defining two clocks).

I know nothing about Altera but the Xilinx toolset really doesn't like multiple clocks. Anything you can do to make them one clock with an enable will really help the tool. Not only will timing improve but run times will go down too as the tool doesn't try to do hold fixing.

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Re: Genesis / Megadrive core ported to MiST

Post by jotego »

Yes, the issue comes from having multiple clocks. The original author of FPGAgen used a sort of clock enable strategy. That actually works fine for small designs. The problem is that we are almost completely using the FPGA resources and then things that are normally not a problem become a problem.

The design is made using a counter on a main 54MHz clock. With that counter there are other signals generated that are sometimes used as clocks directly (which is not a recommended practice) or have a clock enable signal (which is not great either). Again, the two approaches work well with small designs in comparison with the FPGA size.

The FPGA has signal routing and clock routing. The clock routing is optimized to work as a clock across the whole device. The FPGA in MiST has 20 of these global clock trees. Signal routing is optimized for short connections. There seems to be an exception: there is support for reset signals so they go to many more cells. But I do not know how is reset routing done: is it only one? is it many?

When clocks are generated without FPGA clock pins or FPGA PLL outputs, the global clock tree is not used but the regular signal routing. Probably there is some clever instantiation of cells that can be done to force a global clock tree to be used. But we have not figured that out yet. So we have regular routing for clocks. And when regular routing gets full because of true signals then the whole thing starts to break apart.

Up to JT12 v0.3 we were getting clean synthesis normally. Then as I made the sound system larger, or simply different, the fitter started to fail and I have not seen any other clean synthesis. Note that when a design is marginal, it can easily become impractical for the fitter if a single gate is changed in the design.

I do not have experience with making a system as large as the FPGAgen yet. So I do not want to start making big changes to it. For the time being I prefer to wait for robinsonb5 to see if he can fix it. It may actually need a major rewrite of the glue logic that links the two CPUs, the video system and the audio system.

This is also related to how people release open source cores. They usually do not come with implementation details. Ideally we would like to know things like:

-clock edge used
-internal clocking scheme and requirements
-SDC constraints
-Timing diagrams to interact with memories and other external elements to the block
-Warning-free HDL code
-Code that follows FPGA design recommendation and not just simulation/ASIC code

With JT51 I could only do the warning-free part. Basically because I was not conscious of the importance of the other elements. With JT12 I have also followed all the recommendations from Altera.

By the way, there is a nice book chapter available for free about clocks here. I ended up buying the whole book after reading that chapter...
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Re: Genesis / Megadrive core ported to MiST

Post by ijor »

jotego wrote:The design is made using a counter on a main 54MHz clock. With that counter there are other signals generated that are sometimes used as clocks directly (which is not a recommended practice) or have a clock enable signal (which is not great either). Again, the two approaches work well with small designs in comparison with the FPGA size.
Using a clock enable is actually the recommended way to do it. Mixing clocks and clock enable is not a good idea.

The problem with clock enable is that it consumes more resources, but not nearly as much as when used on ASIC designs. Contrary to ASICs, the FPGA registers have dedicated clock enable logic built in. This doesn't mean that use them is completely free. On this Cyclone family there are two clock enable signals per LAB, you can't have a different clock enable for each register in a LAB. Also you might be already using them as part of a conditional updating of the registers. In such cases Quartus will make some further combinatorial logic to implement the desired behaviour. Say, the physical clock enable would become the AND of your logical clock enable and the conditional value. In some cases this might mean an additional LE (logic element) has to be used. But because FPGA implements combinatorial logic using 3 or 4 way LUTs, in many cases no extra LE is needed.

There is an additional problem when replacing a clock with a clock enable. The phasing changes. From the point of view of the master clock, a signal used directly as a clock updates the target register in THIS cycle. A clock enable would do it on the NEXT cycle. This must be considered.
The FPGA has signal routing and clock routing.... There seems to be an exception: there is support for reset signals so they go to many more cells. But I do not know how is reset routing done: is it only one? is it many? ... When clocks are generated without FPGA clock pins or FPGA PLL outputs, the global clock tree is not used but the regular signal routing.
The clock network can be used for any signal, clock, async reset or whatever. They are normally dedicated for low skew and high fanout signals. And it is not true that it is not used for internally generated clocks. What is happening here, I guess, is that Quartus is trying to help you.

The clock network is slower than the regular interconnect. It is designed for low skew, not for speed. If you have a derived clock, you already are having clock skew issues just as direct consequence of producing the derived clock. Taking the signal up to the clock network, plus the relative slow speed of it, would make the skew even worse.
Probably there is some clever instantiation of cells that can be done to force a global clock tree to be used. But we have not figured that out yet. So we have regular routing for clocks.
There are multiple ways to do that and it depends on the exact Quartus version. But check the "global_signal" option setting.
And when regular routing gets full because of true signals then the whole thing starts to break apart.
Are you sure that is the problem? Modern FPGAs normally have lots of interconnect resources. Normally you run out of logic elements way before you run out of routing resources. Can you post a compilation report, may be the summary at least?

Back again to the clock skew issues. The most important here seems to be to check Quartus TimeQuest reports. Depending on this you might try to fix the problem with different strategies.

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Re: Genesis / Megadrive core ported to MiST

Post by jotego »

This is a summary of a build on the Next branch with all the sound elements commented out, to ease synthesis. Nonetheless it still contains many violations. If I include the sound subsystem things just get worse.

Code: Select all

Flow Status	Successful - Tue Mar 21 14:33:11 2017
Quartus II 64-Bit Version	12.1 Build 243 01/31/2013 SP 1 SJ Full Version
Revision Name	fpgagen
Top-level Entity Name	MIST_Toplevel
Family	Cyclone III
Device	EP3C25E144C7
Timing Models	Final
Total logic elements	16,453 / 24,624 ( 67 % )
Total combinational functions	13,869 / 24,624 ( 56 % )
Dedicated logic registers	6,255 / 24,624 ( 25 % )
Total registers	6321
Total pins	73 / 83 ( 88 % )
Total virtual pins	0
Total memory bits	204,156 / 608,256 ( 34 % )
Embedded Multiplier 9-bit elements	6 / 132 ( 5 % )
Total PLLs	1 / 4 ( 25 % )
Setup Summary

Code: Select all

Clock / Slack / End Point TNS
U00|altpll_component|auto_generated|pll1|clk[0]	-5.301	-158.138	1
U00|altpll_component|auto_generated|pll1|clk[2]	-2.227	-82.843	2
spi_SCK	-1.292	-3.817	3
sd1clk_pin	1.681	0.000	4
sd_read_000	4.431	0.000	5
VCLK	4.574	0.000	6
SPICLK	4.803	0.000	7
ps2_clk	26.015	0.000	8
I do not know what the meaning of End Point TNS is...

Recovery Summary

Code: Select all

Clock / Slack / End Point TNS
U00|altpll_component|auto_generated|pll1|clk[2]	-1.821	-29.232	1
spi_SCK	1.673	0.000	2
U00|altpll_component|auto_generated|pll1|clk[0]	2.867	0.000	3
sd_read_000	4.917	0.000	4
VCLK	5.945	0.000	5
romrd_req	6.168	0.000	6
sd_read_001	7.135	0.000	7
sd_write	7.145	0.000	8
SPICLK	11.834	0.000	9
Worst case timing paths

Code: Select all

-5.301	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[11]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.901	2.454	1
-5.301	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[14]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.901	2.454	2
-5.301	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[1]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.901	2.454	3
-5.301	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[10]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.901	2.454	4
-5.272	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[0]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.926	2.400	5
-5.267	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[15]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.893	2.428	6
-5.267	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[12]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.893	2.428	7
-5.267	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[13]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.893	2.428	8
-5.083	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IO_LDS_N	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-3.331	1.806	9
-5.082	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IO_RNW	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-3.331	1.805	10
-4.715	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IO_A[4]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.958	1.811	11
-4.715	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IO_A[2]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.958	1.811	12
-4.715	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IO_A[3]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.958	1.811	13
-4.714	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IO_A[1]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.958	1.810	14
-4.705	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_D[2]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.924	1.835	15
-4.705	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_D[1]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.924	1.835	16
-4.705	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_D[0]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.924	1.835	17
-4.705	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_D[5]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.924	1.835	18
-4.705	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_D[6]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.924	1.835	19
-4.705	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_D[4]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.924	1.835	20
-4.705	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_D[7]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.924	1.835	21
-4.705	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_D[3]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.924	1.835	22
-4.470	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IOC.IOC_IDLE	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	1.622	23
-4.446	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IOC.IOC_T80_ACC	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	1.598	24
-4.414	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IOC.IOC_TG68_ACC	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	1.566	25
-4.391	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[0]	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[0]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.927	1.518	26
-4.282	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[3]	Virtual_Toplevel:virtualtoplevel|T80_IO_D[3]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.925	1.411	27
-4.271	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[6]	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[14]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	1.423	28
-4.260	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[5]	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[13]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.895	1.419	29
-4.221	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[1]	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[1]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	1.373	30
-4.184	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[1]	Virtual_Toplevel:virtualtoplevel|T80_IO_D[1]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.925	1.313	31
-4.158	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[6]	Virtual_Toplevel:virtualtoplevel|T80_IO_D[6]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.925	1.287	32
-4.149	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[7]	Virtual_Toplevel:virtualtoplevel|T80_IO_D[7]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.926	1.277	33
-4.147	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[4]	Virtual_Toplevel:virtualtoplevel|T80_IO_D[4]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.926	1.275	34
-4.145	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[2]	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[10]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	1.297	35
-4.138	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[4]	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[12]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.895	1.297	36
-4.127	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[2]	Virtual_Toplevel:virtualtoplevel|T80_IO_D[2]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.925	1.256	37
-4.125	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IO_SEL	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	1.277	38
-4.123	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[5]	Virtual_Toplevel:virtualtoplevel|T80_IO_D[5]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.926	1.251	39
-4.101	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[3]	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[11]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	1.253	40
-4.089	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[7]	Virtual_Toplevel:virtualtoplevel|TG68_IO_D[15]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.895	1.248	41
-3.828	Virtual_Toplevel:virtualtoplevel|gen_io:io|RD[0]	Virtual_Toplevel:virtualtoplevel|T80_IO_D[0]	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.925	0.957	42
-3.759	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|TG68_IO_DTACK_N	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	0.911	43
-3.758	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|T80_IO_DTACK_N	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	0.910	44
-3.756	Virtual_Toplevel:virtualtoplevel|gen_io:io|FF_DTACK_N	Virtual_Toplevel:virtualtoplevel|IOC.IOC_DESEL	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-2.902	0.908	45
-1.299	virtualtoplevel|VCLK|q	Virtual_Toplevel:virtualtoplevel|TG68_FM_DTACK_N	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-0.304	1.049	46
-1.297	virtualtoplevel|VCLK|q	Virtual_Toplevel:virtualtoplevel|T80_FM_DTACK_N	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-0.304	1.047	47
-1.208	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.302	20.028	48
-1.059	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.319	19.896	49
-1.040	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[3]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.303	19.861	50
-0.989	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.323	19.830	51
-0.978	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[8]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.301	19.797	52
-0.967	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[2]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.276	19.761	53
-0.953	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.284	19.795	54
-0.953	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.284	19.795	55
-0.951	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.290	19.799	56
-0.924	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.287	19.769	57
-0.924	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.287	19.769	58
-0.922	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.293	19.773	59
-0.905	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_low_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.279	19.742	60
-0.905	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_low_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.279	19.742	61
-0.904	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_low_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.285	19.747	62
-0.897	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[13]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	-0.082	19.333	63
-0.890	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[10]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.324	19.732	64
-0.889	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[6]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.298	19.705	65
-0.883	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.288	19.729	66
-0.883	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.288	19.729	67
-0.881	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.294	19.733	68
-0.879	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[3]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	-0.086	19.311	69
-0.873	virtualtoplevel|VCLK|q	Virtual_Toplevel:virtualtoplevel|FMC.FMC_DESEL	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-0.304	0.623	70
-0.871	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[15]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.322	19.711	71
-0.864	virtualtoplevel|VCLK|q	Virtual_Toplevel:virtualtoplevel|FMC.FMC_IDLE_OTERM21	VCLK	U00|altpll_component|auto_generated|pll1|clk[0]	0.056	-0.304	0.614	72
-0.862	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[5]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.303	19.683	73
-0.854	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.291	19.703	74
-0.854	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.291	19.703	75
-0.852	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.297	19.707	76
-0.848	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[8]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.322	19.688	77
-0.835	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_low_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.283	19.676	78
-0.835	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_low_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.283	19.676	79
-0.835	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[9]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.323	19.676	80
-0.834	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_low_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.289	19.681	81
-0.833	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[5]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.324	19.675	82
-0.827	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[4]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[13]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	-0.078	19.267	83
-0.811	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[10]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.303	19.632	84
-0.808	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[11]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.324	19.650	85
-0.792	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[15]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.301	19.611	86
-0.784	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[10]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.289	19.631	87
-0.784	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[10]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.289	19.631	88
-0.782	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[10]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.295	19.635	89
-0.782	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[9]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.302	19.602	90
-0.766	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Equal35~0_OTERM93	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.301	19.585	91
-0.765	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[15]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.287	19.610	92
-0.765	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[15]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.287	19.610	93
-0.763	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[11]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|Flags[2]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.303	19.584	94
-0.763	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[15]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.293	19.614	95
-0.755	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[10]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.292	19.605	96
-0.755	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[10]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_we_reg	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.292	19.605	97
-0.753	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[10]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_0|altsyncram_5od1:auto_generated|ram_block1a0~porta_datain_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.298	19.609	98
-0.749	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[3]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|data_write_tmp[8]	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.324	19.591	99
-0.742	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|opcode[8]	Virtual_Toplevel:virtualtoplevel|TG68:tg68|TG68_fast:TG68_fast_inst|altsyncram:regfile_high_rtl_1|altsyncram_5od1:auto_generated|ram_block1a0~porta_address_reg0	U00|altpll_component|auto_generated|pll1|clk[0]	U00|altpll_component|auto_generated|pll1|clk[0]	18.520	0.287	19.587	100

Code: Select all

-2.227	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[3]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.642	2.783	1
-2.227	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[12]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.642	2.783	2
-2.227	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[13]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.642	2.783	3
-2.215	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[6]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.661	2.752	4
-2.215	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[7]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.661	2.752	5
-2.215	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[9]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.661	2.752	6
-2.181	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[1]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.721	7
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[11]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	8
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[12]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	9
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[13]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	10
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[14]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	11
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[15]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	12
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[16]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	13
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[17]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	14
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[18]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	15
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[19]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	16
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[20]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	17
-2.129	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[21]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.667	18
-2.077	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[3]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.642	2.633	19
-2.077	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[12]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.642	2.633	20
-2.077	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[13]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.642	2.633	21
-2.065	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[6]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.661	2.602	22
-2.065	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[7]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.661	2.602	23
-2.065	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[9]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.661	2.602	24
-2.031	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[1]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.571	25
-2.002	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_req	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.542	26
-2.002	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|boot_req	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.542	27
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[11]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	28
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[12]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	29
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[13]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	30
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[14]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	31
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[15]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	32
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[16]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	33
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[17]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	34
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[18]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	35
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[19]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	36
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[20]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	37
-1.984	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[21]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.522	38
-1.860	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|bootState.BOOT_WRITE_2	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.400	39
-1.852	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_req	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.392	40
-1.852	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|boot_req	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.392	41
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[1]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	42
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[2]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	43
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[3]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	44
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[4]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	45
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[5]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	46
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[6]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	47
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[7]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	48
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[8]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	49
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[9]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	50
-1.842	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_a[10]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.382	51
-1.831	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[0]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.743	52
-1.831	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[4]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.743	53
-1.831	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[5]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.743	54
-1.831	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[8]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.743	55
-1.831	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[10]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.743	56
-1.831	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[11]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.743	57
-1.831	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[14]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.743	58
-1.831	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[15]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.743	59
-1.767	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|bootState.BOOT_WRITE_2	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.307	60
-1.718	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|bootState.BOOT_READ_1	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.258	61
-1.716	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|bootState.BOOT_WRITE_1	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.256	62
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[1]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	63
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[2]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	64
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[3]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	65
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[4]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	66
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[5]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	67
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[6]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	68
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[7]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	69
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[8]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	70
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[9]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	71
-1.692	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_a[10]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.232	72
-1.681	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[0]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.593	73
-1.681	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[4]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.593	74
-1.681	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[5]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.593	75
-1.681	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[8]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.593	76
-1.681	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[10]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.593	77
-1.681	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[11]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.593	78
-1.681	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[14]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.593	79
-1.681	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[15]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.286	2.593	80
-1.568	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|bootState.BOOT_READ_1	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.108	81
-1.566	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|bootState.BOOT_WRITE_1	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.658	2.106	82
-1.551	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|romwr_d[2]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.272	2.477	83
-1.401	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|romwr_d[2]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.272	2.327	84
0.071	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM379_OTERM479	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|spi_interface:spi|sd_shift[0]_OTERM511	spi_SCK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-4.280	4.907	85
0.080	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM379_OTERM483	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|spi_interface:spi|sd_shift[0]_OTERM511	spi_SCK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-4.280	4.898	86
0.191	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|CtrlROM:mysplitrom|CtrlROM_ROM1:myrom1|altsyncram:ram_rtl_0|altsyncram_5ur1:auto_generated|ram_block1a8~porta_we_reg	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|zpu_core_flex:zpu|memAAddr[4]	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.430	8.637	87
0.191	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|CtrlROM:mysplitrom|CtrlROM_ROM1:myrom1|altsyncram:ram_rtl_0|altsyncram_5ur1:auto_generated|ram_block1a8~porta_we_reg	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|zpu_core_flex:zpu|memAAddr[3]	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.430	8.637	88
0.217	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|OnScreenDisplay:myosd|DualPortRAM_2Read_Unreg:charram|altsyncram:ram_rtl_0|altsyncram_nrg1:auto_generated|ram_block1a0~portb_address_reg0	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|OnScreenDisplay:myosd|CharROM_ROM:charrom|Mux0~447_OTERM491	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.003	9.038	89
0.347	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|CtrlROM:mysplitrom|CtrlROM_ROM1:myrom1|altsyncram:ram_rtl_0|altsyncram_5ur1:auto_generated|ram_block1a8~portb_we_reg	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|zpu_core_flex:zpu|decodedOpcode.Decoded_Emulate	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	0.003	8.914	90
0.422	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM379_OTERM485	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|spi_interface:spi|sd_shift[0]_OTERM511	spi_SCK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-4.280	4.556	91
0.426	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM381_OTERM503	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|spi_interface:spi|sd_shift[0]_OTERM511	spi_SCK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-4.280	4.552	92
0.443	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|CtrlROM:mysplitrom|CtrlROM_ROM1:myrom1|altsyncram:ram_rtl_0|altsyncram_5ur1:auto_generated|ram_block1a4~porta_we_reg	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|zpu_core_flex:zpu|memAAddr[4]	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.432	8.383	93
0.443	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|CtrlROM:mysplitrom|CtrlROM_ROM1:myrom1|altsyncram:ram_rtl_0|altsyncram_5ur1:auto_generated|ram_block1a4~porta_we_reg	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|zpu_core_flex:zpu|memAAddr[3]	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.432	8.383	94
0.468	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|CtrlROM:mysplitrom|CtrlROM_ROM2:myrom2|altsyncram:ram_rtl_0|altsyncram_umr1:auto_generated|ram_block1a0~porta_we_reg	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|zpu_core_flex:zpu|memAAddr[4]	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.434	8.356	95
0.468	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|CtrlROM:mysplitrom|CtrlROM_ROM2:myrom2|altsyncram:ram_rtl_0|altsyncram_umr1:auto_generated|ram_block1a0~porta_we_reg	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|zpu_core_flex:zpu|memAAddr[3]	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.434	8.356	96
0.474	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM379_OTERM481	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|spi_interface:spi|sd_shift[0]_OTERM511	spi_SCK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-4.280	4.504	97
0.513	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM381_OTERM497	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|spi_interface:spi|sd_shift[0]_OTERM511	spi_SCK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-4.280	4.465	98
0.515	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|CtrlROM:mysplitrom|CtrlROM_ROM1:myrom1|altsyncram:ram_rtl_0|altsyncram_5ur1:auto_generated|ram_block1a8~porta_we_reg	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|OnScreenDisplay:myosd|DualPortRAM_2Read_Unreg:charram|altsyncram:ram_rtl_1|altsyncram_uai1:auto_generated|ram_block1a0~portb_address_reg0	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.057	8.726	99
0.524	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|OnScreenDisplay:myosd|DualPortRAM_2Read_Unreg:charram|altsyncram:ram_rtl_0|altsyncram_nrg1:auto_generated|ram_block1a0~portb_address_reg0	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|OnScreenDisplay:myosd|CharROM_ROM:charrom|q_OTERM465_OTERM179_OTERM277_OTERM359	U00|altpll_component|auto_generated|pll1|clk[2]	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-0.023	8.711	100

Code: Select all

-1.292	sd_card:sd_card_d|altsyncram:cid_rtl_0|altsyncram_jrc1:auto_generated|ram_block1a0~portb_address_reg0	sd_card:sd_card_d|sd_sdo~14_OTERM519	sd_read_000	spi_SCK	9.260	-5.103	5.437	1
-0.988	sd_card:sd_card_d|altsyncram:buffer_rtl_0|altsyncram_vuc1:auto_generated|ram_block1a0~portb_address_reg0	sd_card:sd_card_d|sd_sdo~12_OTERM517	sd_read_000	spi_SCK	9.260	-5.091	5.145	2
-0.738	sd_card:sd_card_d|altsyncram:csd_rtl_0|altsyncram_jrc1:auto_generated|ram_block1a0~portb_address_reg0	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM381_OTERM499	sd_read_000	spi_SCK	9.260	-5.105	4.881	3
-0.278	sd_card:sd_card_d|altsyncram:csd_rtl_0|altsyncram_jrc1:auto_generated|ram_block1a0~portb_address_reg0	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM381_OTERM503	sd_read_000	spi_SCK	9.260	-5.105	4.421	4
-0.195	sd_card:sd_card_d|altsyncram:csd_rtl_0|altsyncram_jrc1:auto_generated|ram_block1a0~portb_address_reg0	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM379_OTERM481	sd_read_000	spi_SCK	9.260	-5.105	4.338	5
-0.121	sd_card:sd_card_d|altsyncram:csd_rtl_0|altsyncram_jrc1:auto_generated|ram_block1a0~portb_address_reg0	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM379_OTERM479	sd_read_000	spi_SCK	9.260	-5.105	4.264	6
-0.106	sd_card:sd_card_d|altsyncram:csd_rtl_0|altsyncram_jrc1:auto_generated|ram_block1a0~portb_address_reg0	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM381_OTERM497	sd_read_000	spi_SCK	9.260	-5.105	4.249	7
-0.099	sd_card:sd_card_d|altsyncram:csd_rtl_0|altsyncram_jrc1:auto_generated|ram_block1a0~portb_address_reg0	sd_card:sd_card_d|sd_sdo_OTERM31_OTERM251_OTERM305_OTERM379_OTERM485	sd_read_000	spi_SCK	9.260	-5.105	4.242	8
Recovery

Code: Select all

-1.821	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[0]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.359
-1.821	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.359
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[1]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[2]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[3]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[4]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[5]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[6]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[7]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[8]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[9]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[10]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[11]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[12]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[13]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[14]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.706	user_io:user_io_d|status[0]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[15]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.664
-1.671	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[0]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.209
-1.671	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.660	2.209
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[1]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[2]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[3]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[4]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[5]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[6]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[7]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[8]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[9]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[10]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[11]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[12]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[13]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[14]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
-1.556	user_io:user_io_d|but_sw[1]	Virtual_Toplevel:virtualtoplevel|CtrlModule:mycontrolmodule|reset_counter[15]	SPICLK	U00|altpll_component|auto_generated|pll1|clk[2]	9.260	-8.240	2.514
Unconstrained paths

Code: Select all

Property/setup/hold
Illegal Clocks	0	0	1
Unconstrained Clocks	3	3	2
Unconstrained Input Ports	2	2	3
Unconstrained Input Port Paths	139	139	4
Unconstrained Output Ports	22	22	5
Unconstrained Output Port Paths	46	46	6
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Re: Genesis / Megadrive core ported to MiST

Post by ijor »

jotego wrote:This is a summary of a build on the Next branch ...
I understand this is a completely different core than the one we were talking about earlier, right?

Code: Select all

[b]Setup Summary[/b]
Clock / Slack / End Point TNS
U00|altpll_component|auto_generated|pll1|clk[0]	-5.301	-158.138	1
I do not know what the meaning of End Point TNS is...
TNS stands for Total Negative Slack. Is the summatory of the negative slack for all the failing paths on that clock. It gives you an idea of how serious the problem is. In the quoted line above it means that you have, at least (might be much more), about 30 failing paths on that clock. Note that clock skew usually produces hold timing violations, not setup ones, but ...

Code: Select all

Property/setup/hold
Illegal Clocks	0	0	1
Unconstrained Clocks	3	3	2
You have to constrain the clocks, otherwise the report is not really meaningful. Launch standalone TimeQuest. It will tell you all the clocks on the design. And it will help you building the right constraints. Clocks produced by the PLLs can be constrained automatically. Derived clocks might need a manual declaration, which in turn might require some code analysis and/or simulation. Let me know if you need further help with constraining the clocks.

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jotego
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Re: Genesis / Megadrive core ported to MiST

Post by jotego »

ijor wrote:
jotego wrote:This is a summary of a build on the Next branch ...
I understand this is a completely different core than the one we were talking about earlier, right?
No, it is the same FPGAgen core. It's just that there is the master branch and the Next branch in the repository. The Next is where I put new stuff before merging into the master branch.

Thanks a lot for the advise :D
We'll try constraining the other clocks.
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Re: Genesis / Megadrive core ported to MiST

Post by ijor »

jotego wrote:No, it is the same FPGAgen core.
Ah, ok, i was misled by the fact that in this case you are using only 67%. So it means the sound system takes quite a lot, I guess.

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Re: Genesis / Megadrive core ported to MiST

Post by Sorgelig »

jotego wrote:

Code: Select all

Device	EP3C25E144C7
i think it's better to change to C8 part in project settings to help Quartus measure timings more correct.
MiST uses C8 grade of FPGA.

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Re: Genesis / Megadrive core ported to MiST

Post by lips2k15 »

Does this core work in 15khz now? And with sound? It's just this thread is a little chaotic to follow!

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Re: Genesis / Megadrive core ported to MiST

Post by phoboz »

lips2k15 wrote:Does this core work in 15khz now? And with sound? It's just this thread is a little chaotic to follow!
Yes this core has sound:
https://github.com/jotego/jt12/blob/mas ... 20v0.3.rbf

For 15khz put this file on your sdcard along with the core:
https://github.com/phoboz/fpgagen/blob/ ... PGAGEN.CFG

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Re: Genesis / Megadrive core ported to MiST

Post by ijor »

Sorgelig wrote:
jotego wrote:

Code: Select all

Device	EP3C25E144C7
i think it's better to change to C8 part in project settings to help Quartus measure timings more correct.
MiST uses C8 grade of FPGA.
Well spotted! Yes, it is essential. Otherwise you might get a compile build and a timing analysis that targets a faster speed grade and might fail on the shipped product.

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Re: Genesis / Megadrive core ported to MiST

Post by jotego »

ijor wrote:
Sorgelig wrote:
jotego wrote:

Code: Select all

Device	EP3C25E144C7
i think it's better to change to C8 part in project settings to help Quartus measure timings more correct.
MiST uses C8 grade of FPGA.
Well spotted! Yes, it is essential. Otherwise you might get a compile build and a timing analysis that targets a faster speed grade and might fail on the shipped product.
Definitely that was a hidden problem. Thanks!
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Sheldon
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Re: Genesis / Megadrive core ported to MiST

Post by Sheldon »

Hello,

Any news ?
Computers : Mega STE+(4Mo +HXC SLim and UltraSatan), Atari 1040 STe+( 4Mo + HXC SLim and UltraSatan), Atari 1040 Stf+(HXC SLim , Mega ST1+(HXC SLim and UltraSatan), FPGA Mist+Mistery Core( and other ...)
http://www.amedia-computer.com

seastalker
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Re: Genesis / Megadrive core ported to MiST

Post by seastalker »

:) I too have been checking back on this thread for updates.

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