Search found 1671 matches

by slingshot
Tue Apr 09, 2019 8:14 am
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

... but on the schematic, it's a latch and not so straightforward for me - the latch gate input gets the inverted value of the clock, that's why I assumed it works on the negative edge. It gets the inverted clock, but that latch is low active. See that the name of the control signal of the latch is...
by slingshot
Mon Apr 08, 2019 9:00 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

Yepp, just all was running on negedge, but the latch holding the load signal (PQ029) operated on positive edge I'm not so familiar with this chip as I am with the ST version, but that doesn't sound right. I think you are misinterpreting the internal clock inversion in the LT2 cell. The clock is inv...
by slingshot
Mon Apr 08, 2019 1:09 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

Note that the interlace logic has a bug and interlace is always disabled. See this thread for more details: http://www.atari-forum.com/viewtopic.php?f=15&t=30303 I'm running the simulations with interlace = 0 currently. Is it always 1? All the counter bits change on the same edge of the clock. The ...
by slingshot
Mon Apr 08, 2019 11:21 am
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

Note that V ss is ground = 0, not 1. With 0, it's much better! PAL - 1-127 = 508 CPU clocks NTSC - 2-127 = 504 CPU clocks Mono - 73-127 = 220 CPU clocks Somewhere 1 clock is lost (+4 cpu cycles). Upd.: assumed the LT2 module changes its output on falling edge. But using rising edge will allow the c...
by slingshot
Mon Apr 08, 2019 10:53 am
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

No problem at all, just I want to avoid people to have false hopes :)
by slingshot
Mon Apr 08, 2019 10:34 am
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

I would recommend checking other sources. For example see Troed's wiki article about GLUE's state machine. Note that the article is written from a software programmer point of view: https://temlib.org/AtariForumWiki/index.php/ST_STE_Scanlines Thanks! It's more human-consumable for sure. But I've st...
by slingshot
Mon Apr 08, 2019 6:34 am
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

I would ask you to have some patience please. Maybe I made a mistake to announce this work publicly, it was too early. It's not for public use. I only wanted to know if the external interfaces - which I cannot test - are still working. Better to forget this branch for a while. If someone wants to tr...
by slingshot
Sun Apr 07, 2019 3:29 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

The schematic of the STE GSTMCU (combining GLUE and MCU) is available: https://www.chzsoft.de/asic-web/ (scroll down for the download). Thanks! I guess it couldn't be more authentic source for information. I started to process these schematics, I wonder why they have two counters/H/V - one for sync...
by slingshot
Sun Apr 07, 2019 1:09 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

MMU asserts DTACK even earlier. But the CPU doesn't require data to be actually ready as soon as DTACK is asserted. The CPU latches the data at the end of the bus cycle, long after DTACK was detected. Don't want to open another thread, and would like to ask: is there any public info available about...
by slingshot
Sat Apr 06, 2019 9:22 pm
Forum: 680x0
Topic: Open top border
Replies: 17
Views: 13050

Re: Open top border

I have a hardware related question about opening vertical borders: as it comes with changing syncmode, the line lengths (in cycles) are also changed? Because then it would result in tilted lines on TVs and montiors. Or the timings of the syncmode change happens in a way that horizontal counter decis...
by slingshot
Sat Apr 06, 2019 1:16 pm
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

Pacmania works now, the bug was just with the Microwire device. But still a lot to do in the Shifter area. The problem is my knowledge about the machine is not in the same level as @MasterOfGizmo or @ijor.
by slingshot
Fri Apr 05, 2019 9:57 am
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

Committed a change, maybe fixes the serial out. Ethernec is not a surprise, it wasn't modified for the differences of the TG68K and FX68K bus.
Maybe you can try parallel port again, the FPGA sends out the parallel data to the ARM if I set the USB I/O: parallel option in the OSD System menu.
by slingshot
Thu Apr 04, 2019 5:15 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

Make sense. I assumed at S4 there must be valid data already available for a read, as DTACKn has to be asserted for a 0 wait state cycle.
by slingshot
Thu Apr 04, 2019 1:31 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12113

Re: RAM write wait states

I was able to implement the correct memory wait state, and this made me wonder about the 250ns CPU RAM cycle. If a CPU does a read at the start of this time slot, then a following write can only happen at the second half of the RAM cycle (since the CPU sets up a read in 1 cycle, but a write in 2). H...
by slingshot
Thu Apr 04, 2019 12:48 pm
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

RealLarry wrote:Oh, dammit, just tried a usb2serial->nullmodem->PC w/ RS232 and it just works. Nice! Will try to up- and download more MIDI files by ZMODEM now.
Wow! Then ACIA is OK :)
by slingshot
Thu Apr 04, 2019 12:46 pm
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

Next will be serial function. You were speaking of external serial and parallel ports. Do you mean the emulation of serial and parallel ports (MiST->USB cable->PC) or real ones, like usb2serial converters and usb2iee1284 (centronics interface)? I'm not sure how the MiST firmware handles them, they'...
by slingshot
Thu Apr 04, 2019 9:45 am
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

I'm just listening to some MIDI files via real MIDI out. Setup is TOS 1.62 on STeroids, Cubase Lite from A: and MIDI device is a Casio GZ-50M. Working as normal. Wonderful listening... Great! It would be wise to test in normal mode, not STEroids, e.g. see the beauty of cycle-accurancy in some place...
by slingshot
Thu Apr 04, 2019 8:35 am
Forum: MiST
Topic: Genesis / Megadrive core ported to MiST
Replies: 966
Views: 221757

Re: Genesis / Megadrive core ported to MiST

This might be interesting. The 'Eurogamer' review of the Analogue Mega SG (FPGA Megadrive). https://www.eurogamer.net/articles/digitalfoundry-2019-analogue-mega-sg-review We have only 115/122 of the VDP FIFO test passing :) But on MiST, with ROM-RAM-VIDEO RAM shared in one SDRAM chip, it's already ...
by slingshot
Thu Apr 04, 2019 8:23 am
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

RealLarry wrote:I own all these ports and neccessary tools and I'm willing to start some tests at coming weekend. Are there specific options to enable before compiling or are all these great options enabled by default?
.
Nothing, should work from the git repo.
by slingshot
Wed Apr 03, 2019 8:23 pm
Forum: MiST
Topic: Genesis / Megadrive core ported to MiST
Replies: 966
Views: 221757

Re: Genesis / Megadrive core ported to MiST

Fixed:
https://github.com/mist-devel/mist-bina ... 190403.rbf
Thanks for reporting!

Also Direct Color DMA demos are working now.
E.g.: http://www.mediafire.com/file/4k63ahq4l ... mabmp4.zip
by slingshot
Wed Apr 03, 2019 4:52 pm
Forum: MiST
Topic: Updated ST Core?
Replies: 56
Views: 10244

Re: Updated ST Core?

It's not that bad now.

CPU and Memory speeds are correct (fast DMA is no problem):
Photo0037.jpg
Spectrum512 image:
Photo0038.jpg
by slingshot
Wed Apr 03, 2019 11:59 am
Forum: MiST
Topic: Atari800 .com files
Replies: 4
Views: 1789

Re: Atari800 .com files

I think .com make sense if it's loaded by the DOS. Doing the same work externally what DOS should do when loading it is not very appealing (similar to the situation with .PRG files on C=).
by slingshot
Wed Apr 03, 2019 9:53 am
Forum: MiST
Topic: How actively are you using your MiST?
Replies: 94
Views: 19679

Re: How actively are you using your MiST?

A lot of the code of the MiST is written inside processes. It is not optimized at all for size (neither for performance). But it's good enough for old platform. You can write both combinatorial and sequential code inside an "always" or "process" block. And it doesn't matter at all if you write this...
by slingshot
Wed Apr 03, 2019 8:16 am
Forum: MiST
Topic: How actively are you using your MiST?
Replies: 94
Views: 19679

Re: How actively are you using your MiST?

Thenesis wrote:
Also the current implementation of the Atari ST uses a lot of FPGA resources because it uses a lot of processes instead of combinatorial circuits.
You're comparing apples with oranges here. A "process" (it's more like a term in VHDL) can contain combinatorial and sequential logic, too.
by slingshot
Tue Apr 02, 2019 2:09 pm
Forum: MiST
Topic: Mist and an audio input... is it possible?
Replies: 64
Views: 20404

Re: Mist and an audio input... is it possible?

After a while you'll get tired of that flickering 50-60 Hz CRT screen :)
@DrOG I wonder after the increased shunt resistor, it still doesn't accept lower levels.

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