Search found 1672 matches

by slingshot
Sun Apr 28, 2019 5:33 pm
Forum: MiST
Topic: MIST C64 core
Replies: 323
Views: 103369

Re: MIST C64 core

Great! I guess that small difference comes from rounding error in the PLL's parameters. I don't think it would affect tape loading, probably there's larger differences in real datasette speeds.
by slingshot
Sun Apr 28, 2019 1:26 pm
Forum: MiST
Topic: MIST C64 core
Replies: 323
Views: 103369

Re: MIST C64 core

nippur72 wrote: What I don't get is why TAP loading did not have this problem since it uses the same `cass_read` wire/signal.
Added a synchronizer to UART_RX, it fixes all errors for me in the serial input.
by slingshot
Sun Apr 28, 2019 12:09 pm
Forum: MiSTer
Topic: MidiLink 2.0 looking for testers. (no MIDI devices required)
Replies: 345
Views: 80573

Re: MidiLink 2.0 looking for testers. (no MIDI devices required)

Could it also be metastability problem like you described with earlier versions of the Minimig core? I was getting a warning message about timing requirements not being met. That is the same change I thought I was getting better results with, but then I'd recompile and have totally different result...
by slingshot
Sat Apr 27, 2019 2:44 pm
Forum: MiSTer
Topic: MidiLink 2.0 looking for testers. (no MIDI devices required)
Replies: 345
Views: 80573

Re: MidiLink 2.0 looking for testers. (no MIDI devices required)

Release 20190425 seems to fix the issue :) I don't see any CIA changes in that release :) But I've finally could try on MiST, via an RS232-USB adapter, and with this patch, it worked better: https://github.com/mist-devel/mist-board/commit/e7a752de867fb18206b7edaddf452c5bfe221220 But maybe it was ju...
by slingshot
Sat Apr 27, 2019 2:40 pm
Forum: MiST
Topic: MIST C64 core
Replies: 323
Views: 103369

Re: MIST C64 core

DrOG wrote:Setting the 'User port' option to UART in the menu, loading does not start at all.
Of course. Because UART mode is for this:
Photo0057.jpg
Photo0056.jpg
by slingshot
Sat Apr 27, 2019 10:50 am
Forum: MiST
Topic: MIST C64 core
Replies: 323
Views: 103369

Re: MIST C64 core

@nippur72 I've did a little change for CIA's flag_n, it works better in UART mode. Seems doesn't affect TAP playback, but maybe also better (or worse?) for external playback.
by slingshot
Sat Apr 27, 2019 10:43 am
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

@theflynn49 Everything's fine now, thanks!
by slingshot
Fri Apr 26, 2019 7:38 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

I can update the MiST version before a release, it's not urgent to fix it.
by slingshot
Fri Apr 26, 2019 7:28 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

theflynn49 wrote:now this is funny.

very good catch, thank you slingshot :D
Found the same solution, so it must be correct :)
But I'll leave the USE_SP64 thing for you!
by slingshot
Fri Apr 26, 2019 7:27 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

Sorgelig wrote:did i release it too early?
If you enable the border, you'll get a garbage column at the left if it's not masked.
by slingshot
Fri Apr 26, 2019 7:13 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

Yepp, as I see, your changes moved the background from the range of 0-255 (inclusive) to 1-256. But then x==0 should be the border color then. Like this in vdp_main.vhd - if ((x>48 and x<=208) or (gg='0' and x<=256)) and + if ((x>48 and x<=208) or (gg='0' and x>=1 and x<=256)) and PS: that worked. N...
by slingshot
Fri Apr 26, 2019 6:56 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

The same bug with the left column is there with SMSFLY_MIST_20190427.rbf. I can say it's buggy when the left column is not masked. X==0 is the bogus column, but it really should be the first one. I noticed you've changed hblank_end from 511 to 0, but it was there because if you set hblank at 0, it'l...
by slingshot
Fri Apr 26, 2019 6:52 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

theflynn49 wrote:about the x=0 position, there is a x<8 hide column thing (vdp_main line 131)

which sources did you use to recompile the core ?
Just found out that column_mask and pal are not connected correctly in the MiST toplevel. But correcting them won't fix the issues. Will try from your repo.
by slingshot
Fri Apr 26, 2019 6:34 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

I've drawn a red line where x==0. That position should be the first displayed column (at least it was when I last worked on the core). Now seems it's no more at zero position, and what's most interesting, it's not even consistent: Photo0049.jpg Photo0050.jpg Also shows the missing sprite without USE...
by slingshot
Fri Apr 26, 2019 6:13 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

Both NTSC and PAL mode shows the artifact, with or without scandoubler. Note that I'm using MiST, and borders are always on. But this should not make a difference.

And just another strange issue :)
if I not define USE_SP64 to speed up synthesis, many normal sprites will missing.
//`define USE_SP64
by slingshot
Fri Apr 26, 2019 4:49 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

I just tried it, I can't reproduce, sorry. Could you be more specific ? Do you have this on other games ? Didn't notice it in R-Type anymore, but here's in Alf: alfbug2.jpg Note that little brown line on the left, which comes from Alf's finger from the right: alfbug1.jpg I know this was fixed once....
by slingshot
Fri Apr 26, 2019 4:06 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

theflynn49 wrote:@slingshot : which core did you use ? I think I fixed that.
Tried the current MiSTer repo (with mapper lock), the left column bug still there. Check with the Alf game. It's not the sprites, but the background.
by slingshot
Fri Apr 26, 2019 12:24 pm
Forum: MiSTer
Topic: Archie core enchancements
Replies: 3
Views: 1145

Re: Archie core enchancements

I think VIDC doesn't know its master clock frequency, so might be a fixed divisor. The datasheet only says it's typically 24MHz. Implementing the SFR register?
by slingshot
Fri Apr 26, 2019 11:35 am
Forum: MiST
Topic: MIST C64 core
Replies: 323
Views: 103369

Re: MIST C64 core

The ZX ROM loader is not sensitive to polarity at all, so it might work, while C= fail.
by slingshot
Thu Apr 25, 2019 9:30 pm
Forum: MiSTer
Topic: SMS core
Replies: 142
Views: 39134

Re: SMS core

The extra column at the left side is also obvious in the Alf game for example. And there the upper part is fixed scroll area in some screens, which is extended by one pixel to the left. So I guess the problem is only that column must be part of the border. Reverting x<=232 to 233 in vdp_background f...
by slingshot
Thu Apr 25, 2019 9:02 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12117

Re: RAM write wait states

I see. Meanwhile I've finished with the sync, blank and DE generators, uploaded there: https://github.com/gyurco/gstmcu I couldn't upload the waveform output, because it's 10MB zipped. But it's easy to run if Verilator is already installed. Just make, and run ./gstmcu (it'll generate about a dozen f...
by slingshot
Thu Apr 25, 2019 2:39 pm
Forum: MiST
Topic: FPGA64 - C64
Replies: 84
Views: 16159

Re: FPGA64 - C64

Maybe there's some filter on that monitor, which blurs the motion? Is it TV/monitor combo?
by slingshot
Thu Apr 25, 2019 1:24 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12117

Re: RAM write wait states

Another question about hardware scroll: on STE, DE always activated 16 pixels earlier? Because on the 4081S schematic, if the scroll register set to 0, then it's delayed by 4 cycles (=16 pixels), so it'll be 80 cycles long, as supposed to be on the original ST. If scroll != 0, then DE starts 4 cycle...
by slingshot
Wed Apr 24, 2019 4:41 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12117

Re: RAM write wait states

... those tons negations always confuse my mind). Not only yours :) Good to see, I'm not alone :) Another strangeness (at least for me) - vsync length is only 1 line in mono mode? (in color it's 3 lines, which is perfect). Yes, that's correct. Btw, I forgot to mention, although you probably already...
by slingshot
Wed Apr 24, 2019 2:52 pm
Forum: Hardware
Topic: RAM write wait states
Replies: 59
Views: 12117

Re: RAM write wait states

Yes, I should be careful, but mostly the sim seems legit (and I could make errors in it easily - those tons negations always confuse my mind).

Another strangeness (at least for me) - vsync length is only 1 line in mono mode? (in color it's 3 lines, which is perfect).

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