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I use a similar structure for MiST/SiDi cores and MiSTer, but if we agree on a specific structure for MiST (and its clones) I can adapt to it. As you said, Slingshot, it could be a nice contribution from people selling clones.

As you may know, MiSTer users enjoy an update script that grabs everything for them RBF, MRA... (even ROM files!). There are several of these scripts (most of them based on the same original one) and an update all script that calls them and adds more functionality. The update_all script can even upd...

I wonder if Gyurco has an interest in producing a Falcon core. Apparently, some people would actually use it to produce music. I could chip in with the DSP chip if help is needed. This is a long term thing, but I'm just touching base.

The 48MHz change did create some havoc in the DMA part of the CPS-A chip, which runs at 4MHz and the way I was synchronizing it to produce the 4MHz wasn't perfect before, and it is less perfect now. So it has created some artefacts. I have to re-write it a bit so it will meet the original 4MHz timin...

If you don't experience slowdowns, then no problem, as it probably will introduce more wait states to the CPUs in some cases. SDRAM lag increases by ~50% at 48MHz compared to 96MHz. That's about 146ns for each access. Because of the small 64-bit cache, there is an immediate response rather often fo...

slingshot wrote: ↑Sun Jan 10, 2021 1:37 pm Totally green on my MiST @96MHz, with 0 shift (on MiST, it doesn't use DDIO at all, right?)

No, I'm not using it. I will move the SDRAM clock to c[0] eventually if only to avoid the message from Quartus.

I made a mem test core for interleaved bank access. It seems to detect more fails than the clock-frequency based approach of the official test. But no tool is perfect, and this one will have its false negatives too. While doing it, I was looking at the phase of the SDRAM clock and compared both meth...

I don't see how it could help, as zero delay buffer mode is only for aligning the output clock with the input. AFAIK it's not even possible on MiST, since the dedicated PLL input is not the CLOCK_27 for PLL_1 (where it should be put, since it has the dedicated clock output to SDRAM_CLK). If it work...

I know that you can get away with no shift for the SDRAM clock in MiST, at least for low frequencies. However, sometimes it is convenient to have it. The PLL output problem is that it is compensated for at the PLL, not at the pin. Thus there will be PVT (Process, Voltage, Temperature) variation obse...

I happened to try the 4ma drive strength change on another core a week or so back (de10-lite, MAX10 FPGA) and it fixed an occasional crash problem I was having there, so I tried doing a CPS1 build with the same change. DanyPPC tried it, and it seemed to improve matters a little, but wasn't a comple...

After publishing the post, I realised I hadn't included all the capacitance in the path. I was just thinking of the SDRAM. I have been a bit obsessed with the SDRAM for the last two weeks or so... So for 4mA, the edges will be a bit slower than I stated above because of the FPGA output pin capacitan...

About the refresh rate, I normally just run refresh during vertical blanking when no device request access. As there is a small cache for CPUs, that's actually a lot of blanking. I can include a counter for that in simulation to check if rows get refreshed appropriately. Still, given the number of p...

As you may know, I have had some bad experiences with the SDRAM on MiSTer. I have summarized them https://misterfpga.org/viewtopic.php?f=29&t=1727 . MiST works much better in that sense. I have only measured VDD ripple on my board and was acceptable. There was a post here about some problems with th...

Yes, it's a standard thing to open a row and issue commands to different banks together (it's called bank-interleaving). Minimig used that for ages. Just need to care about avoiding clashes on the data bus, and some timing constraints (like tRRD). Also don't forget that the DQM for reads must be ac...

I'm happy to run tests on my MiST too - it's a pre-release board so I guess it'd be a statistical outlier. But if the core passes IO timing (and the timing constraints are correct, of course) then messing with the phase shift shouldn't be necessary. The only other thing that occurs to me - are you ...

That looks very similar to what arcade systems need. Literally, a small, fixed-size, memory to be read on boot up and to be stored on certain events. The file name could be derived, like the names for .CONF files are being derived at the moment. Is the file name for the Archie core fixed in firmware...

Hi,

I need to dump to the SD card the contents of a small EEPROM used in a core. Could you point me to information about how to interface with the firmware to save and read to a file? The core is an arcade so the name of the file could just be derived from the ARC file, I suppose.

Thank you,
jotego

So it's lucky if a core works or not on your machine. 8O I think a standard is needed in development, and perhaps MiST has differences in various version. This is not a good thing to hear for a retro-fan. :( As neither I or I assume neither Jotego has a hardware test lab, we can only test it on lim...

I am implementing it now. It works like a charm!

That’s brilliant. NOP cycles are there to give time to the SDRAM core to get the data out indeed. The SDRAM periphery can still work then! I didn’t know that. Is that a standard thing? I wonder if some manufacturers block the SDRAM interface while waiting for data. I can leave the 32-bit burst lengt...

I just saw this tweet and I got curious: https://twitter.com/sentientsixp/status/1302467733943132160?s=20 Is there anybody who only has a MiST and never upgraded to a MiSTer? If so, why? I have 2 Misters, 3 Misticas, 1 Sidi and 1 Mist, each one on a own setup Mist and 2 Misticas bought used at very...

slingshot wrote: ↑Wed Nov 18, 2020 11:48 am That's cool. If you run out of SDRAM bandwitdh, I have some ideas how to double that in the current controller.

I'm certainly a bit short of bandwidth for CPS 1.5 already. I haven't thought about how to solve it yet. Please share your ideas, here or by e-mail. I am eager to hear them.

Just a happy note for MiST users: I have synthesized CPS1.5 with QSound for the first time, it fits well in MiST (~80% usage).
So there is a good chance CPS2 will fit in MiST too.

Wow! Thank you.
Do I need a firmware update to test it? Or do I just compile it?

@jotego, you already earned the right to request anything. It's also implemented in Genesis for MiST, too, and also enabled in several arcade cores (in Gehstock's repo). Adding it to MiSTery is not complicated, just also a firmware mod is needed for the menu. Thank you! I am interested on this effe...