Search found 253 matches
- Tue Feb 02, 2021 12:02 pm
- Forum: MiST
- Topic: update script for MiST
- Replies: 12
- Views: 632
Re: update script for MiST
I use a similar structure for MiST/SiDi cores and MiSTer, but if we agree on a specific structure for MiST (and its clones) I can adapt to it. As you said, Slingshot, it could be a nice contribution from people selling clones.
- Mon Feb 01, 2021 1:37 pm
- Forum: MiST
- Topic: update script for MiST
- Replies: 12
- Views: 632
update script for MiST
As you may know, MiSTer users enjoy an update script that grabs everything for them RBF, MRA... (even ROM files!). There are several of these scripts (most of them based on the same original one) and an update all script that calls them and adds more functionality. The update_all script can even upd...
- Sun Jan 10, 2021 5:25 pm
- Forum: MiST
- Topic: From MiSTery to a Falcon core?
- Replies: 8
- Views: 570
From MiSTery to a Falcon core?
I wonder if Gyurco has an interest in producing a Falcon core. Apparently, some people would actually use it to produce music. I could chip in with the DSP chip if help is needed. This is a long term thing, but I'm just touching base.
- Sun Jan 10, 2021 5:23 pm
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
Re: CPS2 in MiST
The 48MHz change did create some havoc in the DMA part of the CPS-A chip, which runs at 4MHz and the way I was synchronizing it to produce the 4MHz wasn't perfect before, and it is less perfect now. So it has created some artefacts. I have to re-write it a bit so it will meet the original 4MHz timin...
- Sun Jan 10, 2021 5:20 pm
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
Re: CPS2 in MiST
If you don't experience slowdowns, then no problem, as it probably will introduce more wait states to the CPUs in some cases. SDRAM lag increases by ~50% at 48MHz compared to 96MHz. That's about 146ns for each access. Because of the small 64-bit cache, there is an immediate response rather often fo...
- Sun Jan 10, 2021 5:17 pm
- Forum: MiST
- Topic: Zero-delay buffer mode for SDRAM PLL
- Replies: 9
- Views: 546
- Sat Jan 09, 2021 9:33 pm
- Forum: MiST
- Topic: Zero-delay buffer mode for SDRAM PLL
- Replies: 9
- Views: 546
Re: Zero-delay buffer mode for SDRAM PLL
I made a mem test core for interleaved bank access. It seems to detect more fails than the clock-frequency based approach of the official test. But no tool is perfect, and this one will have its false negatives too. While doing it, I was looking at the phase of the SDRAM clock and compared both meth...
- Wed Jan 06, 2021 7:29 am
- Forum: MiST
- Topic: Zero-delay buffer mode for SDRAM PLL
- Replies: 9
- Views: 546
Re: Zero-delay buffer mode for SDRAM PLL
I don't see how it could help, as zero delay buffer mode is only for aligning the output clock with the input. AFAIK it's not even possible on MiST, since the dedicated PLL input is not the CLOCK_27 for PLL_1 (where it should be put, since it has the dedicated clock output to SDRAM_CLK). If it work...
- Sun Jan 03, 2021 9:42 am
- Forum: MiST
- Topic: Zero-delay buffer mode for SDRAM PLL
- Replies: 9
- Views: 546
Zero-delay buffer mode for SDRAM PLL
I know that you can get away with no shift for the SDRAM clock in MiST, at least for low frequencies. However, sometimes it is convenient to have it. The PLL output problem is that it is compensated for at the PLL, not at the pin. Thus there will be PVT (Process, Voltage, Temperature) variation obse...
- Sun Dec 27, 2020 4:35 pm
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
Re: CPS2 in MiST
I happened to try the 4ma drive strength change on another core a week or so back (de10-lite, MAX10 FPGA) and it fixed an occasional crash problem I was having there, so I tried doing a CPS1 build with the same change. DanyPPC tried it, and it seemed to improve matters a little, but wasn't a comple...
- Sun Dec 27, 2020 4:34 pm
- Forum: MiST
- Topic: Max current setting for SDRAM pins
- Replies: 4
- Views: 313
Re: Max current setting for SDRAM pins
After publishing the post, I realised I hadn't included all the capacitance in the path. I was just thinking of the SDRAM. I have been a bit obsessed with the SDRAM for the last two weeks or so... So for 4mA, the edges will be a bit slower than I stated above because of the FPGA output pin capacitan...
- Sat Dec 26, 2020 6:23 pm
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
Re: CPS2 in MiST
About the refresh rate, I normally just run refresh during vertical blanking when no device request access. As there is a small cache for CPUs, that's actually a lot of blanking. I can include a counter for that in simulation to check if rows get refreshed appropriately. Still, given the number of p...
- Sat Dec 26, 2020 5:48 pm
- Forum: MiST
- Topic: Max current setting for SDRAM pins
- Replies: 4
- Views: 313
Max current setting for SDRAM pins
As you may know, I have had some bad experiences with the SDRAM on MiSTer. I have summarized them https://misterfpga.org/viewtopic.php?f=29&t=1727 . MiST works much better in that sense. I have only measured VDD ripple on my board and was acceptable. There was a post here about some problems with th...
- Tue Dec 15, 2020 6:53 pm
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
Re: CPS2 in MiST
Yes, it's a standard thing to open a row and issue commands to different banks together (it's called bank-interleaving). Minimig used that for ages. Just need to care about avoiding clashes on the data bus, and some timing constraints (like tRRD). Also don't forget that the DQM for reads must be ac...
- Thu Dec 10, 2020 2:40 pm
- Forum: MiST
- Topic: NEW OR UPDATED ARCADE CORES
- Replies: 965
- Views: 254321
Re: NEW OR UPDATED ARCADE CORES
I'm happy to run tests on my MiST too - it's a pre-release board so I guess it'd be a statistical outlier. But if the core passes IO timing (and the timing constraints are correct, of course) then messing with the phase shift shouldn't be necessary. The only other thing that occurs to me - are you ...
- Wed Dec 09, 2020 7:15 pm
- Forum: MiST
- Topic: SD Card interface
- Replies: 4
- Views: 392
Re: SD Card interface
That looks very similar to what arcade systems need. Literally, a small, fixed-size, memory to be read on boot up and to be stored on certain events. The file name could be derived, like the names for .CONF files are being derived at the moment. Is the file name for the Archie core fixed in firmware...
- Wed Dec 09, 2020 6:23 pm
- Forum: MiST
- Topic: SD Card interface
- Replies: 4
- Views: 392
SD Card interface
Hi,
I need to dump to the SD card the contents of a small EEPROM used in a core. Could you point me to information about how to interface with the firmware to save and read to a file? The core is an arcade so the name of the file could just be derived from the ARC file, I suppose.
Thank you,
jotego
I need to dump to the SD card the contents of a small EEPROM used in a core. Could you point me to information about how to interface with the firmware to save and read to a file? The core is an arcade so the name of the file could just be derived from the ARC file, I suppose.
Thank you,
jotego
- Sun Dec 06, 2020 12:02 pm
- Forum: MiST
- Topic: NEW OR UPDATED ARCADE CORES
- Replies: 965
- Views: 254321
Re: NEW OR UPDATED ARCADE CORES
So it's lucky if a core works or not on your machine. 8O I think a standard is needed in development, and perhaps MiST has differences in various version. This is not a good thing to hear for a retro-fan. :( As neither I or I assume neither Jotego has a hardware test lab, we can only test it on lim...
- Sun Nov 29, 2020 3:46 pm
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
Re: CPS2 in MiST
I am implementing it now. It works like a charm!
- Sat Nov 21, 2020 5:02 am
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
Re: CPS2 in MiST
That’s brilliant. NOP cycles are there to give time to the SDRAM core to get the data out indeed. The SDRAM periphery can still work then! I didn’t know that. Is that a standard thing? I wonder if some manufacturers block the SDRAM interface while waiting for data. I can leave the 32-bit burst lengt...
- Thu Nov 19, 2020 8:58 pm
- Forum: MiST
- Topic: Do you still use a MiST exclusively?
- Replies: 48
- Views: 4464
Re: Do you still use a MiST exclusively?
I just saw this tweet and I got curious: https://twitter.com/sentientsixp/status/1302467733943132160?s=20 Is there anybody who only has a MiST and never upgraded to a MiSTer? If so, why? I have 2 Misters, 3 Misticas, 1 Sidi and 1 Mist, each one on a own setup Mist and 2 Misticas bought used at very...
- Thu Nov 19, 2020 8:56 pm
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
Re: CPS2 in MiST
I'm certainly a bit short of bandwidth for CPS 1.5 already. I haven't thought about how to solve it yet. Please share your ideas, here or by e-mail. I am eager to hear them.
- Sat Nov 14, 2020 5:37 pm
- Forum: MiST
- Topic: CPS2 in MiST
- Replies: 55
- Views: 2970
CPS2 in MiST
Just a happy note for MiST users: I have synthesized CPS1.5 with QSound for the first time, it fits well in MiST (~80% usage).
So there is a good chance CPS2 will fit in MiST too.
So there is a good chance CPS2 will fit in MiST too.
- Wed Nov 11, 2020 2:50 pm
- Forum: MiST
- Topic: It's no more a MiSTery
- Replies: 459
- Views: 96031
Re: It's no more a MiSTery
Wow! Thank you.
Do I need a firmware update to test it? Or do I just compile it?
Do I need a firmware update to test it? Or do I just compile it?
- Tue Nov 10, 2020 9:05 pm
- Forum: MiST
- Topic: It's no more a MiSTery
- Replies: 459
- Views: 96031
Re: It's no more a MiSTery
@jotego, you already earned the right to request anything. It's also implemented in Genesis for MiST, too, and also enabled in several arcade cores (in Gehstock's repo). Adding it to MiSTery is not complicated, just also a firmware mod is needed for the menu. Thank you! I am interested on this effe...