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Ah, I see... so before I go nuts trying to create 1152x640, 1088x612 or 960x540 with P96Mode... would firmware changes be needed? :) If your monitor can recognise those modes then you should be able to create them in P96Mode. In 16-bit modes the pixel clock can be 113.44MHz / n, where n is an integ...

PEBCAK as usual - I had somehow managed to copy out minimig.card from the dev branch intsead of master :) 16bit modes work fine now, allthough it seems impossible to make a 1280x720 one, though it's awesome that OSD is now centered on that resolution as well :) Good to hear it's working now! Yeah, ...

So, I finally got around to install Quartus II 13.1 web edition and build the core myself, from your git repo (master branch) :) I was of course hoping to get 16bit modes (using updated minimig.card also from your repo), but no success - I just get dark gray screens on RTG. So I am curious, does it...

Does Lotharek not have stock any more? Or does he not ship to the UK?

You're right that if the input clock is 27MHz, it cannot be aligned with a 48 or 96MHz clock. This technique would need to cascade two PLLs, so the second PLL is used exclusively for the phase shift. That may be needed anyway if a clock tree is to be the path of choice. Is c0 the only PLL output go...

Well, I have many a time done fork by accident. :) I did once accidentally create a website. (In the geocities days I was single-stepping through the process so I could talk someone else through it, and went one step too far!) And I am sure some do it to have a “backup” in case original repo vanish...

Phew, right - but mr. 5017 is ahead of what's released on the mist-binary repo, with his fancy 16bit RTG modes and wav player stuff... hehe :D LOL! To be fair I don't think I ever got round to telling slingshot about the 16-bit mode (in terms of code it's a pretty trivial patch) - I had other tweak...

What could be more important to use c0, not c2 for the SDRAM clock, since it's the direct output port to the pin (but in reality, it doesn't seem to make much difference). Quartus does seem to be smart enough to take care of that automatically - I see this in the CPS1 build log: Info (176353): Auto...

(hope you detected the sarcasm) :lol: I'm taking a different approach with this port from the previous one - I'm trying to make the firmware and controller as MiST-like as possible so it effectively just "wraps" the MiST core with minimal changes. Should making porting other cores easier in future,...

I was able to make hi-res mode work, so it's time to retire the old core. The new one is at the usual place: https://github.com/mist-devel/mist-binaries/tree/master/cores/pcengine Awesome! I've tried a number of games and everything seems to work great, but I'm seeing some minor graphical corruptio...

Than maybe you can add the CD parts, too :) Otherwise you can disable the CD, and instantly get 32KB BRAM from the FIFO. One step at a time, but yes, that would be nice. I've got 15 M9Ks free now, anyway: https://github.com/robinsonb5/TurboGrafx16_NoSoC/tree/tc64 (And the channels are mixed at full...

I'm making some progress porting this core to hostless platforms - I can load a ROM with hardcoded path, (Afterburner II is currently running in attract mode.) Need to implement some input handling and figure out how much firmware I can implement in the limited RAM. There's a .c program in voltab/ d...

Did a full test of all earlier mentioned games with jtcps1-3ns and a small test (5min. play of 1941) with jtcps1+1ns_4ma, but all is good. Have to prepare some other games if further tests has to be dispatched. Thanks, it's appreciated. If we're able to find a combination of settings that works for...

I've been scratching my head over the error messages I see if I try enabling slew rate control or series termination - I found the answer in the Cyclone III device handbook: "You cannot use the programmable slew rate feature when using the 3.0-V PCI, 3.0-V PCI-X, 3.3-V LVTTL, and 3.3-V LVCMOS I/O st...

@robinsonb5 This latest core, Street Fighter 2 World Warrior freeze immediately. OK, that's actually good - if you can make a problem worse you can learn more about it! It lends weight to the theory that the problem's on the output rather than the input side - which is also good because we have nex...

but core interface works always with F12. Just to be clear, does that apply to all the core versions, or just this latest test core? (I think it's always been the case, but worth clarifying.) Just for the hell of it, here's a core with quite a large phase shift (3ns, and still at full drive strengt...

(oops, clicked reply instead of edit - ignore)

About the refresh rate, I normally just run refresh during vertical blanking when no device request access. As there is a small cache for CPUs, that's actually a lot of blanking. I can include a counter for that in simulation to check if rows get refreshed appropriately. That would be a good idea -...

I don't recommend the SDRAM path, it's overcrowded already. Maybe that FIFO can be reduced (or if you don't need the CD, then eliminate fully). Thanks, that's useful to know. I can see one M9K that's only got a couple of hundred bits in use - if I ramstyle="logic" that then I've got 8 M9Ks which gi...

Yes, M9K: 59 / 66 ( 89 % ) Maybe you can squeeze in a control ROM :) Plenty of room if all it needs to do is load a game ROM. If it's going to load a more capable firmware in spare SDRAM it's a bit more of a squeeze, because I'd really need a small cache too. Maybe I need to re-write some SD-card c...

Oh very nice - really cool!

Are there any M9Ks left? (That's the reason I never backported the improvement to the other core to the Chameleon - nowhere for a boot ROM!)

Yes, 13.1 is OK. Sorry, I don't think I can explain easily how to adjust the SDRAM_CLK's phase shift, and jotego's cores are even a bit more tricky, as the QSF is setup by a (Linux) script. There are instructions in his repo how to compile cores, try to follow them, if you have a problem in a speci...

Street Fighter II - World Warrior is one of cps1 games that just freeze my MiST. It's a good game for test. Interestingly that one runs fine for me but the graphics are scrambled. I guess I must have a bad romset. And the the core CPS1_C0 doesn't solve the problem. :( Well it was worth a try. If yo...

Maybe worth to try: the PLL1_CLKOUTp pin (which feeds the SDRAM's CLK input) is a dedicated output to PLL1. However direct output is only possible from the PLL's c0 output. As I see, c2 is used now, which will add some extra delay to the clock. Using c0 would be more correct, and maybe helps. I thi...

Sorry I am going to have to call for help setting this up :oops: . There is mention of .arc files but I don't get those generated. I am not sure if the notes are out-of-date? You need the mra utility which you can find here: https://github.com/sebdel/mra-tools-c - it creates both .ROM and .ARC file...