R4MS wrote:From what I understand, he wants to run the CPU emulation on an ARM core (which goes on a daughter-board of the FPGA-Arcade) and use FPGA only for the custom chips. This will not be a core in the strict FPGA sense, but will most probably faster than anything you could do on an affordable FPGA. Maybe this could be ported our MISTer, since we already have a spare ARM core
Currently we have the FX (cycle accurate core) and the M68K soft core 020 which runs at 28MHz with I/D cache (it's a tidy up of the T68K, nothing major). I have a daughterboard with a real 060. This replaces the soft CPU when used.
For R2 we have these options as well as a new softcore in design which should be approximately equal to the Vampire - except fully open.
You are correct with the hybrid emulation - except it is running on the ARM core in the FPGA. You could do the same think yes on the DE10 I think.
There is a lot of Xilinx specific code in my design, especially in the cache system. Part of the work towards R2 is replacing this with platform specific code, which opens up the possibility of a DE10 port.
Lots of this kinda stuff which needs to be migrated.
attribute RLOC of fd_dq_t2_ena : label is "X1Y0";
attribute U_SET of fd_dq_t2_ena : label is "dram_mux";
-- falling edge reclock
fd_dq_t1_ena_1 : FD_1 port map (Q => dq_ena_t1_1 , C => i_clk, D => dq_ena); -- falling edge clock
fd_dq_t1_ena : FD port map (Q => dq_ena_t1, C => i_clk, D => dq_ena);
fd_dq_t2_ena_1 : FD_1 port map (Q => dq_ena_t2_1 , C => i_clk, D => dq_ena_t1_1);
fd_dq_t2_ena : FD port map (Q => dq_ena_t2, C => i_clk, D => dq_ena_t1);
fd_sel0 : FD port map (Q => dq_sel(0), C => i_clk, D => i_cal_sel(0));
fd_sel1 : FD port map (Q => dq_sel(1), C => i_clk, D => i_cal_sel(1));
lut4_dq_mux1 : LUT4
generic map ( INIT => x"F0CA" )
port map ( I0 => dq_ena_t1_1, I1 => dq_ena_t1, I2 => dq_sel(0), I3 => '0', O => dq_mux_01 );