Did a little sketch.
Cacheable area: 4MB
Cache size: 64KB
Given that the DataSRAM (not on sketch) is 64KByte in size A[15..2] are connected to the address pins of the SRAM used for storing the Tag. So A[21..16] form up the Tag that needs to be stored/read. So these address bits are connected to the data I/Os of the TagSRAM.
On a write the address is always
stored in the TagRAM (red
) and on reads the stored Tag (green
) is compared to the actual A[21..16]. This results in the MATCH being active or not. This is just a very rough collection of thoughts and is not complete.
Steve do you agree?