Moderators: Mug UK, Zorro 2, Greenious, spiny, Sorgelig, Moderator Team
Sorgelig wrote:I hope it won't affect the 1280x720i Minimig resolution with 1280x720 HDMI output.
Interlaced modes on consoles aren't that important than on Minimig where interlace modes are the main modes for high resolutions.
Sorgelig wrote:can you tell more about what is ready and what is not. I want to add your PLL adjust module to framework and use single buffer when vsync_adjust is enabled. Will it work?
Grabulosaure wrote:Could you please test the versions there :
http://temlib.org/pub/mister/ascal/
Grabulosaure wrote:The current implementation of pll_hdmi_adj is good enough for a test and for Genesis/Megadrive. It has issues with SNES. It cannot automatically readjust frequency between 50Hz and 60Hz. Fixing that will need a proper mathematical analysis (for example the PLL adjust is proportional to frequency, the scaler output is proportional to time) and characterisation of the PLL (max slew rate, when to reset it, other parameters...). And probably some cooperation with the MiSTer software about frequency settings.
In the Altera/Intel documentation, there is no clear indication that PLL frequency can be adjusted continuously without glitches, without having to reset the PLL (or I didn't find it).
This demo proves that it is possible!
Sorgelig wrote:You can get initial PLL settings from MiSTer as it's already close to what is required for FPS lock. Then finetune it in your PLL adjustment module.
Grabulosaure wrote:The PLL adjust module is inserted between PLL_HDMI_CFG block which reprograms the PLL and your block that generates accesses from the software issued commands.
It snoops accesses to the register "000111" which sets the "M" fractional frequency coefficient and uses it as reference.
Maybe other settings such as "Charge Pump" and "Bandwidth" should be taken into account.
Sorgelig wrote:So you adjust then PLL only once? How you can keep the output from drifting?
Sorgelig wrote:Since this FPS lock thing is already come to non-standard tricks like constant PLL adjust, then it's worth to try other trick. It won't affect the PLL:
Your scaler may check the drifting of output and once it drift by one line, you add one VSync line or remove one VSync line. So scaler will keep the drifting within the one line.
Not sure how many TVs/Monitors will accept it.
Grabulosaure wrote:With a 32bits "M" counter, the Altera PLL tuning can be very precise.
Sorgelig wrote:I've copied your solution to SNES (since i'm working on SNES now) and even in 60Hz it doesn't work well. After some time i start to see tearing in scroll. There is grid scroll test in 240p Suite. Sometimes it happens immediately, so it seems scaler doesn't re-sync it in the beginning for frame.
Code: Select all
@@ -130,7 +130,7 @@ BEGIN
ELSIF phm='0' AND fcpt=2 THEN
-- Frequency adjust
IF off<10 THEN off:=10; END IF;
- dif:=shift_right(mfrac,off);
+ dif:=shift_right(mfrac,off + 1);
diff<=dif;
sign<=lltune_sync(5);
IF off>=18 THEN
@@ -143,7 +143,7 @@ BEGIN
ELSIF phm='1' THEN
-- Phase adjust
IF ofp<5 THEN ofp:=5; END IF;
- dif:=shift_right(mfrac,ofp + 3);
+ dif:=shift_right(mfrac,ofp + 3 + 1);
IF (ofp>=18 OR off<16) AND fcpt=2 AND phcor=0 THEN
phm<='0';
END IF;
Grabulosaure wrote:In the Altera/Intel documentation, there is no clear indication that PLL frequency can be adjusted continuously without glitches, without having to reset the PLL (or I didn't find it). This demo proves that it is possible!
ijor wrote:Might be worth to ask on Intel Forum. Not sure we'll get an authoritative answer. We might get just a not so useful commendation "you should better reset the PLL just in case". But you might be lucky.
ijor wrote:The documentation might be a bit ambiguous, but it does state that the PLL should be reset after reconfiguration. It even recommends to disable the clock output in some cases.
Sorgelig wrote:my experience with Altera/Intel forum show it as useless in case if you ask specific question and want to get clear answer there.
Sometimes you can browse that forum (which has been ruined by intel's redesign recently) and get some clues.
My vsync_adjust option doesn't reset PLL. And reconfiguration always works.
Sorgelig wrote:ijor wrote:The documentation might be a bit ambiguous, but it does state that the PLL should be reset after reconfiguration. It even recommends to disable the clock output in some cases.
My vsync_adjust option doesn't reset PLL. And reconfiguration always works.
Grabulosaure wrote:My hope is that it could be possible to start with K≈0.5, fix the multiplication and division ratios accordingly, then do only fine-tuning of K to keep synchronisation.
Sorgelig wrote:Grabulosaure wrote:My hope is that it could be possible to start with K≈0.5, fix the multiplication and division ratios accordingly, then do only fine-tuning of K to keep synchronisation.
This is not what can be chosen.
Grabulosaure wrote:The PLL VCO can cover a bit more than an octave. It should be possible to avoid values for K too close to 0 and 1.
Sorgelig wrote:Grabulosaure wrote:The PLL VCO can cover a bit more than an octave. It should be possible to avoid values for K too close to 0 and 1.
Not always. PLL Input freq is 50MHz. If output is close to 50,100,150 then K is close to 0(or 1) in any M/C ratio.
Popular frequency 148.50MHz is one of these.
Actually changing M is not harder than K. It's like 33th bit. But Altera doesn't recommend to use K values <0.05 and >0.95.
Sorgelig wrote:By the way, while output performance of ascal is excellent, the input is not that good.
Tried ascal on ZX Spectrum core and got very bad video over HDMI (while VGA output is good).
ZX Spectrum uses common clock 112MHz for the whole core. ce_pix can vary from 7MHz to 56MHz depending on resolution and scandoubler Fx. And even with ce_pix = 7MHz the picture is garbled.
I had to re-clock the video to 56MHz to get correct picture.
So, regardless the CE rate, video clock is limited. SNES uses 85MHz for CLK_VIDEO and video is correct while 112MHz is already too much for ascal.
Code: Select all
@@ -1265,13 +1266,13 @@ BEGIN
------------------------------------------------------
-- Push pixels to downscaling line buffer
- i_lwr<=i_hnp4 AND i_ven5;
+ i_lwr<=i_hnp4 AND i_ven5 AND i_ce;
IF i_lwr='1' THEN
i_lwad<=(i_lwad+1) MOD OHRES;
END IF;
i_ldw<=i_hpix;
- IF i_hnp3='1' AND i_ven4='1' THEN
+ IF i_hnp3='1' AND i_ven4='1' AND i_ce='1' THEN
i_lrad<=(i_lrad+1) MOD OHRES;
END IF;
Sorgelig wrote:I definitely don't like idea of 2 cascaded PLLs. Modification of M is much easier and more clean solution.
Grabulosaure wrote:I will add updates to the M register to allow wider synchronisation ranges, automatic switching between 50Hz and 60Hz.
If seamless updates of the M register don't work, requiring pixel clock frequencies not too close to multiples of 50Hz is, IMHO, an acceptable constraint for those which desperately need low latency on MiSTer.
Users browsing this forum: Facebook [Bot], HouseOfTheEd, nagus and 6 guests