Magnum TTRAM 256MB boards for the TT 030

[frank.lukas]

... can it be that the card is not in order, has a fault ?

[pakman]

Today I've got a 3rd pair of 128MB SIMMs. Original IBM pulled from PS/2 machine. All spec match. Even the voltage of each individual chip is 5V as required.

Only 64MB shows up in Atari.

There are some other pitfalls as well..
Please tell the chip manufacturer and type.
I would like to check the datasheet in more detail.

[1st1]

Today I've got a 3rd pair of 128MB SIMMs. Original IBM pulled from PS/2 machine. All spec match. Even the voltage of each individual chip is 5V as required.

Only 64MB shows up in Atari.

Have you played with the JEDEC-Jumpers like I quoted above?

[1st1]

Hello, any news? I already spent money a year ago, bought PS2-Simms, but still no MagnumTT!

[Guest]

... can it be that the card is not in order, has a fault ?

the tide turns !! seems to only work with very specific ram
as is

no fault just bad firmware
and better ram support is needed

working i hope with pakman to fix this
ill refund anyone not happy to wait till this ram issue is fixed
i will be able to spend more time this weekend holiday
i just dont want to supply too people something not the best
so its a development
so needs time
and agreements i dont have much time

the factory i was dealing with burned down

anyway

ill spend more time over this weekend to fix the issues and better make it happen

if you not happy

i can supply the board for you AS IS
WITH THE ISSUES or refund the £20 payed upfront...

or wait and see what happend with myself and pakman

[pakman]

i can supply the board for you AS IS WITH THE ISSUES or refund the £20 payed upfront...

My proposal:
1. Send the board "as is" to 1st1
2. He will find out whether he can get 256MB with his DRAM
3. If yes: Thats fine!
4. If not: I am offering 1st1 to send the board + DRAM to me for debugging.

@simbo and 1st1:
Any objection?

[Dal]

I'm happy to wait until it's working. This would have been a whole lot easier if the board came pre-populated with 265MB soldered on in my opinion rather than having to chance our luck on getting the right simms.

[Guest]

no probs
i have 6 made up not got a lot of time ill test this weekend

i have 4 days just now with the bank holiday two are set aside to deal with the 3 stbooks im working on


i got two sets of 128s from a member that dont work
to mod fix and i have two sets
one that works as 256 and a set that just shows 128mb
it worked in the last proto board as 256 so its not the design
the magnum is mega fussy. about exact ram
not good!!!
the other problem is adding 3.3v
i believe most modern CPLD will allow 3,3 or 5v i/o
so careful choice of the chip is needed here,.,, and add some current limit incase of an error
will need a jumper to set it over or some jtag flash etc ...??

its not really a problem will just need too add some level shifters
and i think there is 7cm width and 20 cm breadth to spare
so enlarging the board to accommodate the ics
or use smd and mount them and others on the bottom and top
easy stuff...!! keep the board small and the cost is cheeper for miles 1cm allround adds 300 euros to the run
my own board is the older design ive added new sockets too ive fitted PD bypass to
i feel to use auto detect or some non nibble mode {4 bit address chips on the simms}
like edo 60ns moreover easier to find {a needle in a haystack springs too mind}
its just a case to strobe the memory address correctly .....
this has to be interplirated to form the correct addressing for EDO
and is actually quite easy using a few maps code in groups

and we can use standard 60ns edo any ram FPM or EDO
as long as the nibble mode addressing is preserved at the TT
and recoded for the ram used

so i can add a port for jtag and produce another 20
im not worried about slack boards i will built up them anyway

this is the way it goes reworking and reverse engineering designs
rip up and retry at least we have a solid 4 layer design too work from
i can add some space to the left of the board to add flash ports


let me know the additions and ill adjust the proteus design as needed

three heads are better than one for sure...!!!
thanks...
just need it too be the best issue free...
i was just not happy with the detection situation
and feel PD3 and 4 are needed for auto detect
perhaps use two more i/os
and the code
so if you give me details i can install the correct compiler
and im mainly good at finding errors and justify code...

i just dont want too disappoint people.,..

[pakman]

This pdf shows the hardware modification required when using a Lattice M4A5 CPLD instead of a MACH210.

MagTT-01.pdf

[Guest]

ok no probs

ill rework the design and allow for the extra flash port etc

many thanks...

[Guest]

ok most of the mods to the schematic are done

i have a little question

on the pic attached i circled WE and WE1A WE0A
not sure whats ment at this point???

do you mean add both banks Write enable together and ditch separate bank write mask??
to make 1 common WE...?? if so i can remove rework the resistor banks ???

ive done this and removed the WE mask changed the resistors and renamed the simm connections

added the flash socket and the mods
please take a look over and check all is aok

[pakman]

on the pic attached i circled WE and WE1A WE0A
not sure whats ment at this point???

Even if WE1A and WE0A are different pins, the signal is exactly the same for both.
I propose to use only one output pin from the CPLD, and route the signal via the resistor to both SIMMs in parallel.
This saves one pin of the CPLD, which could be used for "future catastrophes"..

[Guest]

on the pic attached i circled WE and WE1A WE0A
not sure whats ment at this point???

Even if WE1A and WE0A are different pins, the signal is exactly the same for both.
I propose to use only one output pin from the CPLD, and route the signal via the resistor to both SIMMs in parallel.
This saves one pin of the CPLD, which could be used for "future catastrophes"..

nice
as i expected.... as the 030 addresses all 64 bits at once via its inbuilt MMU ,,,
and its then up to the cpld to interpret the address blocks and banks ...
possible the signals are 1 step ..nop... apart as the ram used in the magnum needs to symtrical like 32X32 or 64X64
we need to forget the limits and address as one any type as this is what they are all setup too do
you can you can you can but you can by default address them as the same root..type
per ic block.. of 4 nibbles or a word or dword as 32 bit etc far better to set the mmu in the processor to
address the TT ram in a way ... a driver... tsr
not sure that banking is better than shared write
ill check out the original
overall i think get across the board 256 from each type using
normal addressing will work for all 5v types
not sure many types of edo will not work
as most edo thats 3.3v has a regulator on one or both sides
i found a good site to covert two pairs of 64 to one pair of 128MB
http://www.jax184.com/projects/128mb%20simm/simms.html

so the schematic ill check over ......... done looks aok too me so
any other additions pin breakouts what ever???
will i add a board mounted jumper rather than a jumper on the flash socket..
ive tied both banks to WE common and via a 33r to WEX from the pin

so please check it over and the bus labels
im sure its aok as per the addition but as usual ill check again anyway 5 times checks
and annotate it before i shift it over too rework the pcb...
want to be sure before i resize the board etc on four layers
i measured up and plenty of room

moved all the vertical mount through hole res and cap ...to smd 2or 3 mm types
low current so not an issue ill mount them under with thru vias...

[pakman]

possible the signals are 1 step ..nop... apart as the ram used in the magnum needs to symtrical like 32X32 or 64X64

There is also an idea how to support asymmetric DRAM chips as well..

so please check it over and the bus labels
im sure its aok as per the addition but as usual ill check again anyway 5 times checks
and annotate it before i shift it over too rework the pcb...

Sure. Can you please share a *.pdf version of the latest schematics!?

[Guest]

hi

for some reason the pdf didnt attach

[Guest]

There is also an idea how to support asymmetric DRAM chips as well..

so i see AB selectors choice on the MAD buffers
the problem is hardware level disorder

instead of 4 nibbles per block as proper nibble mode {4 bits cas ras we} {4 bits cas ras we} etc itteration
its two banks of 4x4x4 A then 4x4x4 to the other simmB a nop apart so the data by block addressing is 32 bits / 8 but the buffers are hardware set to shift by 4 ..

edo can be used if all 12 bits as a block so the mad addressing at hardware needs to be
mad 1,2,3,4 5,6,7,8 9,10,11,12 A,B and one bank
the buffers serve no purpose as far as my scope says...

it seems to me it was designed with one type and layout of ram in mind
instead of starting from a base FPM and EDO types for the addressing abjections and script to write into

so re interperate the postions of the Mem address per the 3 buffers to something more logical and as a base AB is far better if we have two bits not one this is 4 states... so 12/4 = 3 so we can use non symetic types
the use of the spare io/s


thanks for the help

think the MAD buffers need ripped up and set out correctly

i am going to look up how apple addressed it and make a few questions up
perhaps get some circuits from people... others can help with info here

i think a mac 2 used 68030 controlled ram from its own internal mmu
and some layouts may give up some more details.... its added details for sure




what worries me the most is

if your saying that the two banks WE signals are not one full phase of the clock appart
then this is a portion of code missing

and if this is the case then its simply a noop needs added between the two bank WE signals

this would show up as wired back screens where you would get boot if the correct WE selection

i wonder why you say to be the signals are the same time frame
yet in hardware !!! they are seperate>??

[qq1975b]

one question...as Dal suggested...is not possible to solder ram chips directly on board? modern ram chips. It will avoid looking for working SIMMs.

[Guest]

one question...as Dal suggested...is not possible to solder ram chips directly on board? modern ram chips. It will avoid looking for working SIMMs.

yes it is lets make it work with 256MB and a specific chips bread

then order and solder on 8 chips

takes time
to develop

if anyones not happy with there £20 or more injection that bought the parts
for the older board

ill be happy to refund them

but im not happy to make any boards that only seem to support
some rare as hens teath ram
i would rather rip up and retry with members support
and like amiga sites it works,, as 256MB as we know it can easily

as a 68030 can address up to 32bits data by 32 bits address {mmu controlled 128GB}
but only 12bit addrress is avalible easily to the TTRAM port
we need two more addresses as ram banks of TTram and upper ram
yes use smd ics but not yet

[pakman]

i wonder why you say to be the signals are the same time frame
yet in hardware !!! they are seperate>??

This is why:
Have a look at the original MAGNUM.PDS file:

Code: Select all

PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    TT-RAM Steuerung mit Burst Mode fuer FastPage RAM's
PATTERN 
REVISION 1.15
AUTHOR   Uwe Schneider
COMPANY
DATE     10.12.98

CHIP  _ttram  MACH210

;---------------------------------- PIN Declarations ---------------
....
PIN  30         WE_1                  COMB                       ; OUTPUT
PIN  28         WE_0                  COMB                       ; OUTPUT
....
;----------------------------------- Boolean Equation Segment ------
EQUATIONS
....
/WE_1  = /RW* MemStart
/WE_0  = /RW* MemStart
....

WE_1 and WE_0 are sharing the same equation!

think the MAD buffers need ripped up and set out correctly

We can get rid of the 3x F157 MAD buffers if we are using a M4A5-128/64 (100pin TQFP 0,5mm pitch):
http://www.reichelt.de/GALs-PALs/M4A5-1 ... %2F64-10VN
But do you dare to do the layout and the PCB assembly lateron?

[Guest]

yes

i would just lay out the pcb and get them fabricated in china {cheep}

you can get up to 3 protos you are responsible for components and all designs
they get made in mins.... they can arrive with with the ic mounted and EL tested

so lets do it 100 pin is only 25 per side ... i can handle that easy

one controller no buffer if we use a new family we should make it so it will support also 3.3v i/o in banks
we can use 16 bit smd bi dir selectable level converters if needed
they are like 25mm long and 2.5mm wide... 32 connections to data i/o one switch pin
the address bus can just use a R2R to supply its bias
i think its aok to solder on smd dram without issue
its the right type of dram that size that isnt already on a simm is the issue

not easy for big sizes in older format
some 32 ic + controller or perhaps 16 or hahaha 8 na chance
you need at least 16ics these days to support older 256MB
its not easy...

this is why i say if we use 3.3v dram EDO then its a stip down of the code
to just overall control as there is as you say no need for the bank selectors
however comes the wait state issue
and nibble mode addressing {4bits per ic} double banks interleave ...
so this also needs solved
i wonder why this card was over engineered and imho never completed
was because of density of ram ic avalible

perhaps using a small SSD {any size up to 138GB} instead or perhaps two or four
cuts out the overhead and io count and build in ide generic support
and also runs at a sufficent speed most are very fast 10ns access
and the protocal is easy to implement
just one main controller and a SSD controller

its a solution thats ever expanding up to 138GB,. of TT ram would easily be possible
one thing you can do is say have a 128MB cashe as TT ram 50ns type {printer chips all thats big and fast }



lots to think about before upgrading the design

so my idea of it so far is
a generic 256 or 128MB board with one dimm {old p2/3 style 60ns cas 2.2.2}
and one controller

to this is a small daugher board plug in connect the devices
can have ide and sata has a mount for network



i dont mind to rip it up infact it would be a pleasure...

[Guest]

on a kind of related topic

i notice the mpu in my TT rev K runs hot
above 60deg
so i want to machine a nice metal heatsink and small fan to cool it down
as there is little room to mount a decent multi thin fin heatsink

so
ill draw it up in autocad and make the files avalible cnc etc,...
im not planning to make one for purchase
but ill lodge the design in a cheep remaker so you can order one
its a good idea it isnt easy to replace this ic but its easy to get them for $5 each from HK
i have 5 if you need a mpu for the TT and some older gold top 030

in copper for sure...

[Guest]

man look just so you know im not a dafty
it may come off the same equassion
but its never less.... than one pins and one port itteration away as it will be sent when the relevent port flops
{each itteration of a port flop will take core time delay + 62.5ns}
individual addressing will take core delay + 62.5ns per port flop
so there will be delay between the signals
ill set up the scope and a pair of good 64MB
see what the scope says
if they match exactly then im not sure why the guy bothered with two banks WE
i dont buy it !!
after all the step size at 16mhz of the clock
at control pin level is bus / 16mhz {62.5ns } after all this daft mach210 runs as a clock 16mhz from the TT
far too SLOW!!!!!!! a simple nop takes 62.5ns
so cant be less than 62.5ns X bank pins ..per port per bank
so in the mach 210 there is like 4 individual gals... two banks of two
each bank is 62.5ns and too slow by the time you add core delay and handshake etc nop for wait delay for older machines

so if this was the case as you say we is the very same
each bank is addressed at 125ns... and not 60 hum and not ripple written in 4 bit nibble mode
two banks 62.5ns max.. as per the core clock ...??? no
the WE signals need only be 125ns / bit blocks{4,8,16,32,64} / 2banks so the space between the signals is like 125/ 4 8 16 etc.../ 2
very small some ns appart to address the blocks and not overwrite other data blocks

too this end the only way to reuse TT ram properly is to borrow the 32mhz clock ~31.25ns per step
or use its own ttl 32mhz source ,,,, not sure its better

as it will always run too slow... as is

personally i would like to use the same controller as jookie used in the ultrasatan and good code for ide etc ... in place

its well fast @i think 400mhz and is a wide chip with lots of i/os

and i think maintains compatability
we can use a port expander 8 i/o to 32 i/o dual address data
as its easily fast enought for 8-32 bit translation and mounts the platform at 16bit 32bit ide generic

using this dsp then you can lock an input pin to the 32mhz tt clock ,,,and the bus will follow it...

i think reusing the non logic of the older mach chips and even the whole family
shows non foward thinking
and reusing jookies dsp chip well even two to gain what we all need
is a far better investment of time
as most of the work is already done

ripple nibble mode write is what the TT uses

perhaps some investment is needed by me for one in how the TT bus can be used
and some time in the bog reading on the tablet ....

[pakman]

individual addressing will take core delay + 62.5ns per port flop
so there will be delay between the signals
ill set up the scope and a pair of good 64MB
see what the scope says

Yes, let's see..
You will win a beer if WE_0 and WE_1 signals appear to be different!

each bank is addressed at 125ns... and not 60 hum and not ripple written in 4 bit nibble mode
two banks 62.5ns max.. as per the core clock ...??? no
the WE signals need only be 125ns / bit blocks{4,8,16,32,64} / 2banks so the space between the signals is like 125/ 4 8 16 etc.../ 2

This is what the Lattice simulation tool says:

MagTT-08.tif

1st write access with 0 waitstate, 2nd write access with 1 waitstate, the again 0 waitstate
(btw. in real life you can't switch waitstates on the fly, since it is set by a jumper, but for the simulation I can do)

personally i would like to use the same controller as jookie used in the ultrasatan and good code for ide etc ... in place

Which controller is he using?

[Guest]

C dsp fast core
check out the schematics
i just like the fact most of the work for ide is done

if your sure WE is fine then its cool with me
im just dumb feked why uwe added two pins... it makes no sense...
i ve not looked at the code i have,..
ill check it out bank write nibble order is all that springs to mind
if you read the service manual it mentions this addressing mode
together with 3 other modes the TT uses to engage the TTRAM and also the VME RAM if fitted..
ive not installed any event sims in this machine

so...
think a 400mhz core dsp can use like 8 to 32 bit with 2 bit control
400/ 32... hum

as i say i would rather use two of these ics
as they are c cores something i know like the hairs on my toes...

gives plenty of i/os spare flash etc etc from the machine
c core very easy user programable
and fits to existing work giving access to network also

jookie is there if we get stuck
and he can extend his flash program to fit the bill

not sure he wont be very happy its being exended..

we can reuse with some code help {keep all pin virtual is the rule in this kind of design} 4 port ide
but add sata and pata as a plug in controller board its far better
and allows for usb ide external drives....

above all referance clock must = 32mhz system TT clock or a phase locked sudo

[Guest]

please take a couple of pics of the ram modules you use frank lukas before you flog them...??