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tenox wrote:Today I've got a 3rd pair of 128MB SIMMs. Original IBM pulled from PS/2 machine. All spec match. Even the voltage of each individual chip is 5V as required.
Only 64MB shows up in Atari.
tenox wrote:Today I've got a 3rd pair of 128MB SIMMs. Original IBM pulled from PS/2 machine. All spec match. Even the voltage of each individual chip is 5V as required.
Only 64MB shows up in Atari.
frank.lukas wrote:... can it be that the card is not in order, has a fault ?
simbo2 wrote:i can supply the board for you AS IS WITH THE ISSUES or refund the £20 payed upfront...
simbo2 wrote:on the pic attached i circled WE and WE1A WE0A
not sure whats ment at this point???
pakman wrote:simbo2 wrote:on the pic attached i circled WE and WE1A WE0A
not sure whats ment at this point???
Even if WE1A and WE0A are different pins, the signal is exactly the same for both.
I propose to use only one output pin from the CPLD, and route the signal via the resistor to both SIMMs in parallel.
This saves one pin of the CPLD, which could be used for "future catastrophes"..
simbo2 wrote:possible the signals are 1 step ..nop... apart as the ram used in the magnum needs to symtrical like 32X32 or 64X64
simbo2 wrote:so please check it over and the bus labels
im sure its aok as per the addition but as usual ill check again anyway 5 times checks
and annotate it before i shift it over too rework the pcb...
pakman wrote:There is also an idea how to support asymmetric DRAM chips as well..
qq1975b wrote:one question...as Dal suggested...is not possible to solder ram chips directly on board? modern ram chips. It will avoid looking for working SIMMs.
simbo2 wrote:i wonder why you say to be the signals are the same time frame
yet in hardware !!! they are seperate>??
Code: Select all
PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE TT-RAM Steuerung mit Burst Mode fuer FastPage RAM's
PATTERN
REVISION 1.15
AUTHOR Uwe Schneider
COMPANY
DATE 10.12.98
CHIP _ttram MACH210
;---------------------------------- PIN Declarations ---------------
....
PIN 30 WE_1 COMB ; OUTPUT
PIN 28 WE_0 COMB ; OUTPUT
....
;----------------------------------- Boolean Equation Segment ------
EQUATIONS
....
/WE_1 = /RW* MemStart
/WE_0 = /RW* MemStart
....
simbo2 wrote:think the MAD buffers need ripped up and set out correctly
simbo2 wrote:individual addressing will take core delay + 62.5ns per port flop
so there will be delay between the signals
ill set up the scope and a pair of good 64MB
see what the scope says
simbo2 wrote:each bank is addressed at 125ns... and not 60 humand not ripple written in 4 bit nibble mode
two banks 62.5ns max.. as per the core clock ...??? no
the WE signals need only be 125ns / bit blocks{4,8,16,32,64} / 2banks so the space between the signals is like 125/ 4 8 16 etc.../ 2
simbo2 wrote:personally i would like to use the same controller as jookie used in the ultrasatan and good code for ide etc ... in place
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