Like for prefetch I woud like to share some insights about another emulation problem, it came up (again) while "fixing" Blood Money, this time I try to be more generic. Following is the copy of a text available on my site, I figure it belongs here too.
[edit: you may want to read a further version below instead, though this one is interesting too to see how bizarre theories evolve]
Current version is here:
http://www.atari-forum.com/viewtopic.php?f=94&t=24770&start=25#p229804
Program counter and exception
Scope
This text doesn't describe the full exception process on the M68000 nor even
how the full exception stack frame is built.
You need to check other doc for those aspects.
It is also useful to check doc on prefetch.
The text only focuses on the exact value of the program counter (PC) that is
pushed on the stack when an address or bus error exception occurs.
Sources
- Motorola M68000 Microprocessors User's Manual (http://www.freescale.com)
- Discussions in Atari-Forum (http://www.atari-forum.com)
- wikipedia.org and maybe other web sites
- And of course development of Steem SSE: for this reason, Steem specifics are
discussed.
Why?
This aspect of ST emulation came to attention when it was realised that some
programs work or crash based on that value being correct, mainly in the context
of code protection.
For example, the value pushed on a very low stack would later be executed as
code, which is a rather intricate procedure.
If the value is wrong, the instruction is garbage.
Cases
Need an adjustment:
Blood Money (+2)
Phaleon, European Demos, Transbeauce 2 (-2) (*)
War Heli (+2)
(*) Don't know why but those demos also work without adjustment in the current
build of Steem SSE. This wasn't the case before.
Need no adjustment:
BIG demo
Darkside of the Spoon
(...) many!
User Manual
The M68000 User's Manual states:
"
Value saved for the program counter is advanced 2–10 bytes beyond the address
of the first word of the instruction that made the reference causing the bus
error.
If the bus error occurred during the fetch of the next instruction, the saved
program counter has a value in the vicinity of the current instruction, even
if the current instruction is a branch, a jump, or a return instruction.
"
Based on just that, the programmer who would actually use the pushed PC
couldn't compute it. He had to be lucky or to test on real hardware.
Program Counter
There is only one PC register in the M68000. When a crash occurs, the exact
content of the register at that time is copied, not some fancy value.
So the question is, when the exception happens, what should be the precise
value of the PC?
Fetching
The PC (program counter) points to a word (16bit value) in memory that is
supposed to be fetched.
To fetch a word, the PC value is set on the address bus, and the word is copied
into the IRC processor register.
Increment time
Fetching words in memory implies that the PC regularly is incremented
(PC=PC+2, shortened as 'PC+2') to point to the correct word.
We know that when an instruction starts, PC points to the next word.
That is, it points to the word being currently copied in IRC (prefetch
rule: at the start of any instruction, IRC is loaded with the next instruction
or operand).
It implies that the PC isn't incremented right after the word in memory
has been fetched. After fetching, PC points to the last word having been
fetched.
It is important to know, because we're told:
"
In most processors, PC is incremented after fetching an instruction,
and holds the memory address of (“points to”) the next instruction that
would be executed. (In a processor where the incrementation precedes the
fetch, PC points to the current instruction being executed.)
"
(http://en.wikipedia.org/wiki/Program_counter)
On the M68000, PC also apparently points to the next address, but in reality
it points to a word that has already been fetched.
Note that incrementing PC is computing, which calls on CPU resources.
We can imagine that this computing could compete with other computing,
especially address computing (indexing).
Separation of incrementing and fetching
PC must be incremented before fetching, or the value would be wrong, but this
doesn't tell us when exactly.
At this point we must accept that it may happen just before fetching or some
time before: in that latter case, other operations could be executed between
PC incrementing and fetching.
So for emulation, placing 'PC+2' right at prefetch time wouldn't necessarily
be correct all the time.
To support the idea that incrementing PC and prefetch may be separate
operations, a quote from Motorola:
"A limited arithmetic unit is located in the HIGH and LOW sections, and a
general capability arithmetic and logical unit is located in the DATA
section.
This allows address and data calculations to occur simultaneously. For example,
it is possible to do a register-to-register word addition concurrently with a
program counter increment".
One would guess that the (double) AU is doing the PC+2.
Microcode
All M68000 behaviour is commanded by microcodes, sort of mini-instructions.
This applies to fetching as well. Separation of incrementing and fetching
would mean that distinct microcodes are used for each of those operations.
Prefetch (fetching the next macro-instruction) in the M68000 is commanded by
such microcode, with a code for PC+2 and a code for 'Read word into IRC'.
Where exactly those microcodes are placed depends on the instruction.
Exception
An address or bus error exception may happen during a read or a write cycle
of the current instruction. Read cycles occur before write cycles, but fetch
cycles may occur after write cycles. When the read or write cycle causes an
exception, the value of PC at that time is pushed on the supervisor stack.
That value depends on the placement of the 'PC+2' microcode (which always
comes before prefetch).
Hacks are legit
Since each instruction is uniquely commanded by microcodes, adjusting the PC
for specific instructions (based on opcode) is legit. It would be doubly
so if microcode programming was chaotic in the M68000 (which hasn't been
proved either way yet). But of course, it's annoying to have to wait for bug
reports before such or such instruction is "fixed".
General theory
That's why we may imagine some general rules for the placement of 'PC+2'.
It is just guess work, hence speculative.
The 'PC+2' happens after read cycles (getting the source at <EA> for 'effective
address').
Apparently on the M68000, a generic microcode routine is used to get the
effective address. This implies that 'PC+2' can't happen before or during
getting effective address. Maybe right before reading in some cases? In our
theory we assume the 'get <EA>' routine implies copying data on CPU data lines:
where else would the information be held?
If some fetching is needed to get the destination, the 'PC+2' of prefetch also
happens after that fetching, obviously.
We can't fetch next instruction before fetching all operands of the current
instruction.
But 'PC+2' tends to happen before write cycles if possible, to make sure that
the CPU may prefetch in time, apparently.
If however after fetching operands for the destination, the CPU also must
compute an address like in (d16, An), then it can't compute 'PC+2' at the same
time and it will be delayed until after the write (or maybe during for LONG
operations).
I accept that this theory may be totally wrong. It works with some known cases,
but there aren't so many.
The following points are Steem specific.
Ideal implementation
Imagining that the theory above be correct, the ideal way to implement it
would be to make sure that variable pc is always up-to-date in emulation,
so that when an exception happens, the correct value is copied and we must
do nothing else.
Practically we would add additional macros in cpu.cpp.
In Steem, we have an annoying 'pc+2' right before the instruction begins, in
'm68k_PROCESS'. Now we know that this placement isn't perfect, but it isn't
trivial to undo, as for example 'intercept' functions rely on that behaviour of
pc.
Also, because 'pc+2' is there in the general process loop, we should remove it
and add it in each instruction at the exact right place, which is error prone.
Note that in most cases the right place is just before 'Prefetch IRC'.
This ideal implementation could also very easily handle further idiosyncrasies:
in fact we microcode the behaviour just like on a real M68000.
Temporary implementation
We don't need to do all that to test our theory. It suffices to adapt PC at
exception-time only.
Because Steem considers exceptions concerning the 'DEST' (destination) part
'write' exceptions even if the CPU was reading (which hadn't any consequence
until now), we must test against some opcodes to correct that. We could also
add macros to get correct exception 'action' code, but it's more involved.
We make 'pc+2' if the exception happened during a real write cycle and there's
no indexing needed for destination.
This is what's in the current beta (3.5.1).
Current beta
In Steem SSE (beta), exception stack frame is now handled in two ways:
based on opcodes if option 'Hacks' is checked. This is the more robust way.
Based on a general theory if that option isn't checked. It works with known
cases but could break some programs. It is the 'fun' way.
If we manage the 'ideal implementation', there won't be any 'Hacks' difference
anymore.
PS: the code at sourceforge isn't up-to-date yet
Program counter and exception
Moderators: Mug UK, Steem Authors, Moderator Team
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Steven Seagal
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Program counter and exception
Last edited by Steven Seagal on Wed Apr 29, 2015 5:55 pm, edited 2 times in total.
In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
Re: Program counter and exception
Here's the tables I've generated from a real STE on bus and address errors:
The five rows are:
Cycle count
Fault instruction offset (can't remember exactly how I generated this) / PC offset from start of instruction
Fault code
SR (which may be more luck than judgement)
IR
This is pretty preliminary. I'm not sure the SR row or fault offset have any value. The PC offset and fault codes should be right though.
The five rows are:
Cycle count
Fault instruction offset (can't remember exactly how I generated this) / PC offset from start of instruction
Fault code
SR (which may be more luck than judgement)
IR
This is pretty preliminary. I'm not sure the SR row or fault offset have any value. The PC offset and fault codes should be right though.
Code: Select all
Name : Dn An (A) (A)+ -(A) $(A) I(A) .W .L $(P) I(P) #
ADDRESS error early (A0)
add.w *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
D050 D058 D060 D068 D070 D078 D079 D07A D07B
add.w d0,* *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
D150 D158 D160 D168 D170 D178 D179
adda.w *,a1 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2200 2208 2200 2208 2208 2200 2208
D2D0 D2D8 D2E0 D2E8 D2F0 D2F8 D2F9 D2FA D2FB
add.w #1,* - *60 *60 *64 *64 *68 *64 *68
1/4 1/4 -1/6 3/4 7/4 1/6 1/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2200
0650 0658 0660 0668 0670 0678 0679
addq.w #1,* - - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
5250 5258 5260 5268 5270 5278 5279
addx.w *,* - *60
-1/4
RI5
2200
D348
and.w *,d0 - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2200 2200 2208 2200 2208 2208
C050 C058 C060 C068 C070 C078 C079 C07A C07B
and.w d0,* *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
C150 C158 C160 C168 C170 C178 C179
and.w #1,* - *60 *60 *64 *64 *68 *64 *68
1/4 1/4 -1/6 3/4 7/4 1/6 1/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
0250 0258 0260 0268 0270 0278 0279
clr.w * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
4250 4258 4260 4268 4270 4278 4279
cmp.w *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2200 2208 2200 2208 2208 2200 2208 2200
B050 B058 B060 B068 B070 B078 B079 B07A B07B
cmpa.w *,a1 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
B2D0 B2D8 B2E0 B2E8 B2F0 B2F8 B2F9 B2FA B2FB
cmp.w #1,* - *60 *60 *64 *64 *68 *64 *68
1/4 1/4 -1/6 3/4 7/4 1/6 1/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
0C50 0C58 0C60 0C68 0C70 0C78 0C79
cmpm.w (a0)+,(a1)+ *56
1/4
RI5
2200
B348
eor.w d0,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
B150 B158 B160 B168 B170 B178 B179
eor.w #1,* - *60 *60 *64 *64 *68 *64 *68
1/4 1/4 -1/6 3/4 7/4 1/6 1/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
0A50 0A58 0A60 0A68 0A70 0A78 0A79
move.w *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2208 2208 2200 2208 2200 2200
3010 3018 3020 3028 3030 3038 3039 303A 303B
move.w *,a1 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2200 2200 2208 2200 2208 2208
3250 3258 3260 3268 3270 3278 3279 327A 327B
move.w *,(a1) - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2208 2208 2200 2208 2200 2200
3290 3298 32A0 32A8 32B0 32B8 32B9 32BA 32BB
move.w *,(a1)+ - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2200 2200 2208 2200 2208 2208
32D0 32D8 32E0 32E8 32F0 32F8 32F9 32FA 32FB
move.w *,-(a1) - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2208 2208 2200 2208 2200 2208
3310 3318 3320 3328 3330 3338 3339 333A 333B
move.w *,2(a1) - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 9/2 D/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2200 2208 2200 2208 2208 2200
3350 3358 3360 3368 3370 3378 3379 337A 337B
move.w *,2(a1,d0) - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 9/2 D/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2208 2200 2208 2200 2200 2208
3390 3398 33A0 33A8 33B0 33B8 33B9 33BA 33BB
move.w *,W - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 9/2 D/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2200 2208 2200 2208 2208 2200
31D0 31D8 31E0 31E8 31F0 31F8 31F9 31FA 31FB
move.w *,L - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 B/2 F/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2208 2200 2208 2200 2200 2208
33D0 33D8 33E0 33E8 33F0 33F8 33F9 33FA 33FB
movem.w *,d0-d3 *60 *60 *64 *68 *64 *68 *64 *68
1/6 1/6 3/8 7/4 1/8 1/A 9/8 D/4
RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200
4C90 4C98 4CA8 4CB0 4CB8 4CB9 4CBA 4CBB
movem.w d0-d3,* *60 *60 *64 *68 *64 *68
1/6 -1/6 3/8 7/8 1/8 1/A
WI5 WI5 WI5 WI5 WI5 WI5
2208 2208 2200 2208 2200 2200
4890 48A0 48A8 48B0 48B8 48B9
movep.w d0,4(a1) -
movep.w 4(a0),d0 -
neg.w * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
4450 4458 4460 4468 4470 4478 4479
negx.w * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
4050 4058 4060 4068 4070 4078 4079
not.w * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
4650 4658 4660 4668 4670 4678 4679
or.w *,d0 - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2200 2200 2208 2200 2208 2208
8050 8058 8060 8068 8070 8078 8079 807A 807B
or.w d0,* *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
8150 8158 8160 8168 8170 8178 8179
or.w #1,* - *60 *60 *64 *64 *68 *64 *68
1/4 1/4 -1/6 3/4 7/4 1/6 1/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
0050 0058 0060 0068 0070 0078 0079
sub.w *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2200 2208 2200 2208 2208 2200 2208 2200
9050 9058 9060 9068 9070 9078 9079 907A 907B
sub.w d0,* *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2200
9150 9158 9160 9168 9170 9178 9179
suba.w *,a1 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2208 2200 2208 2200 2200 2208 2200
92D0 92D8 92E0 92E8 92F0 92F8 92F9 92FA 92FB
sub.w #1,* - *60 *60 *64 *64 *68 *64 *68
1/4 1/4 -1/6 3/4 7/4 1/6 1/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
0450 0458 0460 0468 0470 0478 0479
subq.w #1,* - - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
5350 5358 5360 5368 5370 5378 5379
subx.w *,* - *60
-1/4
RI5
2208
9348
tst.w * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
4A50 4A58 4A60 4A68 4A70 4A78 4A79
add.l *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2208 2200 2208 2200 2200 2208
D090 D098 D0A0 D0A8 D0B0 D0B8 D0B9 D0BA D0BB
add.l d0,* *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2208 2200
D190 D198 D1A0 D1A8 D1B0 D1B8 D1B9
adda.l *,a1 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2200 2208 2200 2208 2208 2200
D3D0 D3D8 D3E0 D3E8 D3F0 D3F8 D3F9 D3FA D3FB
add.l #1,* - *64 *64 *68 *68 *72 *68 *72
1/6 1/6 -3/6 3/6 7/6 1/8 1/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
0690 0698 06A0 06A8 06B0 06B8 06B9
addq.l #1,* - - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2200
5290 5298 52A0 52A8 52B0 52B8 52B9
addx.l *,* - *60
-1/4
RI5
2208
D388
and.l *,d0 - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
C090 C098 C0A0 C0A8 C0B0 C0B8 C0B9 C0BA C0BB
and.l d0,* *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
C190 C198 C1A0 C1A8 C1B0 C1B8 C1B9
and.l #1,* - *64 *64 *68 *68 *72 *68 *72
1/6 1/6 -3/6 3/6 7/6 1/8 1/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
0290 0298 02A0 02A8 02B0 02B8 02B9
clr.l * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
4290 4298 42A0 42A8 42B0 42B8 42B9
cmp.l *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2200 2208 2200 2208 2208 2200 2208
B090 B098 B0A0 B0A8 B0B0 B0B8 B0B9 B0BA B0BB
cmpa.l *,a1 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2208 2200 2208 2200 2200 2208 2200
B3D0 B3D8 B3E0 B3E8 B3F0 B3F8 B3F9 B3FA B3FB
cmp.l #1,* - *64 *64 *68 *68 *72 *68 *72
1/6 1/6 -3/6 3/6 7/6 1/8 1/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
0C90 0C98 0CA0 0CA8 0CB0 0CB8 0CB9
cmpm.l (a0)+,(a1)+ *56
1/4
RI5
2208
B388
eor.l d0,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
B190 B198 B1A0 B1A8 B1B0 B1B8 B1B9
eor.l #1,* - *64 *64 *68 *68 *72 *68 *72
1/6 1/6 -3/6 3/6 7/6 1/8 1/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
0A90 0A98 0AA0 0AA8 0AB0 0AB8 0AB9
move.l *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2200 2208 2200 2208 2208 2200 2208 2200
2010 2018 2020 2028 2030 2038 2039 203A 203B
move.l *,a1 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
2250 2258 2260 2268 2270 2278 2279 227A 227B
move.l *,(a1) - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2200 2208 2200 2208 2208 2200 2208 2200
2290 2298 22A0 22A8 22B0 22B8 22B9 22BA 22BB
move.l *,(a1)+ - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
22D0 22D8 22E0 22E8 22F0 22F8 22F9 22FA 22FB
move.l *,-(a1) - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2200 2208 2200 2208 2208 2200 2208 2200
2310 2318 2320 2328 2330 2338 2339 233A 233B
move.l *,2(a1) - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 9/2 D/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
2350 2358 2360 2368 2370 2378 2379 237A 237B
move.l *,2(a1,d0) - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 9/2 D/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2208 2208 2200 2208 2200 2200
2390 2398 23A0 23A8 23B0 23B8 23B9 23BA 23BB
move.l *,W - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 9/2 D/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2200 2200 2208 2200 2208 2208
21D0 21D8 21E0 21E8 21F0 21F8 21F9 21FA 21FB
move.l *,L - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 B/2 F/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2208 2208 2200 2208 2200 2200
23D0 23D8 23E0 23E8 23F0 23F8 23F9 23FA 23FB
movem.l *,d0-d3 *60 *60 *64 *68 *64 *68 *64 *68
1/6 1/6 3/8 7/4 1/8 1/A 9/8 D/4
RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2208 2200 2208 2200 2200 2208
4CD0 4CD8 4CE8 4CF0 4CF8 4CF9 4CFA 4CFB
movem.l d0-d3,* *60 *60 *64 *68 *64 *68
1/6 -1/6 3/8 7/8 1/8 1/A
WI5 WI5 WI5 WI5 WI5 WI5
2200 2208 2208 2200 2208 2200
48D0 48E0 48E8 48F0 48F8 48F9
movep.l d0,4(a1) -
movep.l 4(a0),d0 -
neg.l * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
4490 4498 44A0 44A8 44B0 44B8 44B9
negx.l * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
4090 4098 40A0 40A8 40B0 40B8 40B9
not.l * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
4690 4698 46A0 46A8 46B0 46B8 46B9
or.l *,d0 - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
8090 8098 80A0 80A8 80B0 80B8 80B9 80BA 80BB
or.l d0,* *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
8190 8198 81A0 81A8 81B0 81B8 81B9
or.l #1,* - *64 *64 *68 *68 *72 *68 *72
1/6 1/6 -3/6 3/6 7/6 1/8 1/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
0090 0098 00A0 00A8 00B0 00B8 00B9
sub.l *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2200 2208 2200 2208 2208 2200 2208
9090 9098 90A0 90A8 90B0 90B8 90B9 90BA 90BB
sub.l d0,* *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
9190 9198 91A0 91A8 91B0 91B8 91B9
suba.l *,a1 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -3/2 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2200 2208 2208 2200 2208 2200 2200 2208
93D0 93D8 93E0 93E8 93F0 93F8 93F9 93FA 93FB
sub.l #1,* - *64 *64 *68 *68 *72 *68 *72
1/6 1/6 -3/6 3/6 7/6 1/8 1/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
0490 0498 04A0 04A8 04B0 04B8 04B9
subq.l #1,* - - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
5390 5398 53A0 53A8 53B0 53B8 53B9
subx.l *,* - *60
-1/4
RI5
2200
9388
tst.l * - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -3/2 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
4A90 4A98 4AA0 4AA8 4AB0 4AB8 4AB9
asl.w #1,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
E1D0 E1D8 E1E0 E1E8 E1F0 E1F8 E1F9
asr.w #1,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
E0D0 E0D8 E0E0 E0E8 E0F0 E0F8 E0F9
lsl.w #1,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
E3D0 E3D8 E3E0 E3E8 E3F0 E3F8 E3F9
lsr.w #1,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
E2D0 E2D8 E2E0 E2E8 E2F0 E2F8 E2F9
rol.w #1,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
E7D0 E7D8 E7E0 E7E8 E7F0 E7F8 E7F9
ror.w #1,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
E6D0 E6D8 E6E0 E6E8 E6F0 E6F8 E6F9
roxl.w #1,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
E5D0 E5D8 E5E0 E5E8 E5F0 E5F8 E5F9
roxr.w #1,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
E4D0 E4D8 E4E0 E4E8 E4F0 E4F8 E4F9
bchg #1,* - - - - - - - -
bchg d0,* - - - - - - - -
bset #1,* - - - - - - - -
bset d0,* - - - - - - - -
bclr #1,* - - - - - - - -
bclr d0,* - - - - - - - -
btst #1,* - - - - - - - -
btst d0,* - - - - - - - -
mulu *,d0 - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2200 2208 2208 2200 2208 2200 2200
C0D0 C0D8 C0E0 C0E8 C0F0 C0F8 C0F9 C0FA C0FB
muls *,d0 - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
C1D0 C1D8 C1E0 C1E8 C1F0 C1F8 C1F9 C1FA C1FB
abcd *,* - -
nbcd * - - - - - - - -
sbcd *,* - -
st * - - - - - - - -
tas * - - - - - - - -
move.w sr,* - *56 *56 *60 *60 *64 *60 *64
1/2 1/2 -1/4 3/2 7/2 1/4 1/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
40D0 40D8 40E0 40E8 40F0 40F8 40F9
move.w *,ccr - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2200 2208 2208 2200 2208 2200 2200 2208 2200
44D0 44D8 44E0 44E8 44F0 44F8 44F9 44FA 44FB Re: Program counter and exception
Code: Select all
ADDRESS error late (A1)
add.w *,d0 - - - - - - - - - - - -
add.w d0,* - - - - - - -
adda.w *,a1 - - - - - - - - - - - -
add.w #1,* - - - - - - - -
addq.w #1,* - - - - - - - - -
addx.w *,* - *64
-1/4
RI5
2200
D348
and.w *,d0 - - - - - - - - - - -
and.w d0,* - - - - - - -
and.w #1,* - - - - - - - -
clr.w * - - - - - - - -
cmp.w *,d0 - - - - - - - - - - - -
cmpa.w *,a1 - - - - - - - - - - - -
cmp.w #1,* - - - - - - - -
cmpm.w (a0)+,(a1)+ *60
1/4
RI5
2200
B348
eor.w d0,* - - - - - - - -
eor.w #1,* - - - - - - - -
move.w *,d0 - - - - - - - - - - - -
move.w *,a1 - - - - - - - - - - - -
move.w *,(a1) *56 *56 *60 *60 *64 *64 *68 *64 *68 *64 *68 *60
1/4 1/4 1/4 1/4 1/4 1/6 1/6 1/6 1/8 1/6 1/6 1/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
3280 3288 3290 3298 32A0 32A8 32B0 32B8 32B9 32BA 32BB 32BC
move.w *,(a1)+ *56 *56 *60 *60 *64 *64 *68 *64 *68 *64 *68 *60
1/4 1/4 1/4 1/4 1/4 1/6 1/6 1/6 1/8 1/6 1/6 1/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
32C0 32C8 32D0 32D8 32E0 32E8 32F0 32F8 32F9 32FA 32FB 32FC
move.w *,-(a1) *60 *60 *64 *64 *68 *68 *72 *68 *72 *68 *72 *64
-1/4 -1/4 -1/4 -1/4 -1/4 -1/6 -1/6 -1/6 -1/8 -1/6 -1/6 -1/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71
move.w *,2(a1) *60 *60 *64 *64 *68 *68 *72 *68 *72 *68 *72 *64
3/4 3/4 3/4 3/4 3/4 3/6 3/6 3/6 3/8 3/6 3/6 3/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
3340 3348 3350 3358 3360 3368 3370 3378 3379 337A 337B 337C
move.w *,2(a1,d0) *64 *64 *68 *68 *72 *72 *76 *72 *76 *72 *76 *68
7/4 7/4 7/4 7/4 7/4 7/6 7/6 7/6 7/8 7/6 7/6 7/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
3380 3388 3390 3398 33A0 33A8 33B0 33B8 33B9 33BA 33BB 33BC
move.w *,W *60 *60 *64 *64 *68 *68 *72 *68 *72 *68 *72 *64
1/4 1/4 1/4 1/4 1/4 1/6 1/6 1/6 1/8 1/6 1/6 1/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
31C0 31C8 31D0 31D8 31E0 31E8 31F0 31F8 31F9 31FA 31FB 31FC
move.w *,L *64 *64 *64 *64 *68 *68 *72 *68 *72 *68 *72 *68
1/6 1/6 1/4 1/4 1/4 1/6 1/6 1/6 1/8 1/6 1/6 1/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
33C0 33C8 33D0 33D8 33E0 33E8 33F0 33F8 33F9 33FA 33FB 33FC
movem.w *,d0-d3 - - - - - - - -
movem.w d0-d3,* - - - - - -
movep.w d0,4(a1) -
movep.w 4(a0),d0 -
neg.w * - - - - - - - -
negx.w * - - - - - - - -
not.w * - - - - - - - -
or.w *,d0 - - - - - - - - - - -
or.w d0,* - - - - - - -
or.w #1,* - - - - - - - -
sub.w *,d0 - - - - - - - - - - - -
sub.w d0,* - - - - - - -
suba.w *,a1 - - - - - - - - - - - -
sub.w #1,* - - - - - - - -
subq.w #1,* - - - - - - - - -
subx.w *,* - *64
-1/4
RI5
2208
9348
tst.w * - - - - - - - -
add.l *,d0 - - - - - - - - - - - -
add.l d0,* - - - - - - -
adda.l *,a1 - - - - - - - - - - - -
add.l #1,* - - - - - - - -
addq.l #1,* - - - - - - - - -
addx.l *,* - *68
-1/4
RI5
2208
D388
and.l *,d0 - - - - - - - - - - -
and.l d0,* - - - - - - -
and.l #1,* - - - - - - - -
clr.l * - - - - - - - -
cmp.l *,d0 - - - - - - - - - - - -
cmpa.l *,a1 - - - - - - - - - - - -
cmp.l #1,* - - - - - - - -
cmpm.l (a0)+,(a1)+ *64
1/4
RI5
2208
B388
eor.l d0,* - - - - - - - -
eor.l #1,* - - - - - - - -
move.l *,d0 - - - - - - - - - - - -
move.l *,a1 - - - - - - - - - - - -
move.l *,(a1) *56 *56 *64 *64 *68 *68 *72 *68 *72 *68 *72 *64
1/4 1/4 1/4 1/4 1/4 1/6 1/6 1/6 1/8 1/6 1/6 1/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2208 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
2280 2288 2290 2298 22A0 22A8 22B0 22B8 22B9 22BA 22BB 22BC
move.l *,(a1)+ *56 *56 *64 *64 *68 *68 *72 *68 *72 *68 *72 *64
1/4 1/4 1/4 1/4 1/4 1/6 1/6 1/6 1/8 1/6 1/6 1/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2208 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2208
22C0 22C8 22D0 22D8 22E0 22E8 22F0 22F8 22F9 22FA 22FB 22FC
move.l *,-(a1) *60 *60 *68 *68 *72 *72 *76 *72 *76 *72 *76 *68
-1/4 -1/4 -1/4 -1/4 -1/4 -1/6 -1/6 -1/6 -1/8 -1/6 -1/6 -1/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
2300 2308 2310 2318 2320 2328 2330 2338 2339 233A 233B 233C
move.l *,2(a1) *60 *60 *68 *68 *72 *72 *76 *72 *76 *72 *76 *68
3/4 3/4 3/4 3/4 3/4 3/6 3/6 3/6 3/8 3/6 3/6 3/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
2340 2348 2350 2358 2360 2368 2370 2378 2379 237A 237B 237C
move.l *,2(a1,d0) *64 *64 *72 *72 *76 *76 *80 *76 *80 *76 *80 *72
7/4 7/4 7/4 7/4 7/4 7/6 7/6 7/6 7/8 7/6 7/6 7/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
2380 2388 2390 2398 23A0 23A8 23B0 23B8 23B9 23BA 23BB 23BC
move.l *,W *60 *60 *68 *68 *72 *72 *76 *72 *76 *72 *76 *68
1/4 1/4 1/4 1/4 1/4 1/6 1/6 1/6 1/8 1/6 1/6 1/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
21C0 21C8 21D0 21D8 21E0 21E8 21F0 21F8 21F9 21FA 21FB 21FC
move.l *,L *64 *64 *68 *68 *72 *72 *76 *72 *76 *72 *76 *72
1/6 1/6 1/4 1/4 1/4 1/6 1/6 1/6 1/8 1/6 1/6 1/A
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
23C0 23C8 23D0 23D8 23E0 23E8 23F0 23F8 23F9 23FA 23FB 23FC
movem.l *,d0-d3 - - - - - - - -
movem.l d0-d3,* - - - - - -
movep.l d0,4(a1) -
movep.l 4(a0),d0 -
neg.l * - - - - - - - -
negx.l * - - - - - - - -
not.l * - - - - - - - -
or.l *,d0 - - - - - - - - - - -
or.l d0,* - - - - - - -
or.l #1,* - - - - - - - -
sub.l *,d0 - - - - - - - - - - - -
sub.l d0,* - - - - - - -
suba.l *,a1 - - - - - - - - - - - -
sub.l #1,* - - - - - - - -
subq.l #1,* - - - - - - - - -
subx.l *,* - *68
-1/4
RI5
2200
9388
tst.l * - - - - - - - -
asl.w #1,* - - - - - - - -
asr.w #1,* - - - - - - - -
lsl.w #1,* - - - - - - - -
lsr.w #1,* - - - - - - - -
rol.w #1,* - - - - - - - -
ror.w #1,* - - - - - - - -
roxl.w #1,* - - - - - - - -
roxr.w #1,* - - - - - - - -
bchg #1,* - - - - - - - -
bchg d0,* - - - - - - - -
bset #1,* - - - - - - - -
bset d0,* - - - - - - - -
bclr #1,* - - - - - - - -
bclr d0,* - - - - - - - -
btst #1,* - - - - - - - -
btst d0,* - - - - - - - -
mulu *,d0 - - - - - - - - - - -
muls *,d0 - - - - - - - - - - -
abcd *,* - -
nbcd * - - - - - - - -
sbcd *,* - -
st * - - - - - - - -
tas * - - - - - - - -
move.w sr,* - - - - - - - -
move.w *,ccr - - - - - - - - - - -
Re: Program counter and exception
Code: Select all
BUS error early (A0)
add.w *,d0 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
D050 D058 D060 D068 D070 D078 D079
add.w d0,* *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
D150 D158 D160 D168 D170 D178 D179
adda.w *,a1 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
D2D0 D2D8 D2E0 D2E8 D2F0 D2F8 D2F9
add.w #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -2/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2208
0650 0658 0660 0668 0670 0678 0679
addq.w #1,* - - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
5250 5258 5260 5268 5270 5278 5279
addx.w *,* - *124
-2/4
RI5
2200
D348
and.w *,d0 - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
C050 C058 C060 C068 C070 C078 C079
and.w d0,* *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
C150 C158 C160 C168 C170 C178 C179
and.w #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -2/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
0250 0258 0260 0268 0270 0278 0279
clr.w * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
4250 4258 4260 4268 4270 4278 4279
cmp.w *,d0 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
B050 B058 B060 B068 B070 B078 B079
cmpa.w *,a1 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
B2D0 B2D8 B2E0 B2E8 B2F0 B2F8 B2F9
cmp.w #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -2/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
0C50 0C58 0C60 0C68 0C70 0C78 0C79
cmpm.w (a0)+,(a1)+ *124
0/4
RI5
2200
B348
eor.w d0,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
B150 B158 B160 B168 B170 B178 B179
eor.w #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -2/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
0A50 0A58 0A60 0A68 0A70 0A78 0A79
move.w *,d0 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
3010 3018 3020 3028 3030 3038 3039
move.w *,a1 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
3250 3258 3260 3268 3270 3278 3279
move.w *,(a1) - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
3290 3298 32A0 32A8 32B0 32B8 32B9
move.w *,(a1)+ - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
32D0 32D8 32E0 32E8 32F0 32F8 32F9
move.w *,-(a1) - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
3310 3318 3320 3328 3330 3338 3339
move.w *,2(a1) - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
3350 3358 3360 3368 3370 3378 3379
move.w *,2(a1,d0) - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2200
3390 3398 33A0 33A8 33B0 33B8 33B9
move.w *,W - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
31D0 31D8 31E0 31E8 31F0 31F8 31F9
move.w *,L - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2208
33D0 33D8 33E0 33E8 33F0 33F8 33F9
movem.w *,d0-d3 *128 *128 *132 *136 *132 *136 - -
0/6 0/6 2/8 6/8 0/8 0/A
RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200
4C90 4C98 4CA8 4CB0 4CB8 4CB9
movem.w d0-d3,* *128 *128 *132 *136 *132 *136
0/6 -2/6 2/8 6/8 0/8 0/A
WI5 WI5 WI5 WI5 WI5 WI5
2208 2208 2200 2208 2200 2200
4890 48A0 48A8 48B0 48B8 48B9
movep.w d0,4(a1) -
movep.w 4(a0),d0 *128
4/2
RI5
2200
0108
neg.w * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
4450 4458 4460 4468 4470 4478 4479
negx.w * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
4050 4058 4060 4068 4070 4078 4079
not.w * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
4650 4658 4660 4668 4670 4678 4679
or.w *,d0 - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
8050 8058 8060 8068 8070 8078 8079
or.w d0,* *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
8150 8158 8160 8168 8170 8178 8179
or.w #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -2/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
0050 0058 0060 0068 0070 0078 0079
sub.w *,d0 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
9050 9058 9060 9068 9070 9078 9079
sub.w d0,* *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2200
9150 9158 9160 9168 9170 9178 9179
suba.w *,a1 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
92D0 92D8 92E0 92E8 92F0 92F8 92F9
sub.w #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -2/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
0450 0458 0460 0468 0470 0478 0479
subq.w #1,* - - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
5350 5358 5360 5368 5370 5378 5379
subx.w *,* - *124
-2/4
RI5
2208
9348
tst.w * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
4A50 4A58 4A60 4A68 4A70 4A78 4A79
add.l *,d0 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2200
D090 D098 D0A0 D0A8 D0B0 D0B8 D0B9
add.l d0,* *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2208 2200
D190 D198 D1A0 D1A8 D1B0 D1B8 D1B9
adda.l *,a1 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
D3D0 D3D8 D3E0 D3E8 D3F0 D3F8 D3F9
add.l #1,* - *132 *132 *132 *136 *140 *136 *128
0/6 0/6 -4/6 2/6 6/6 0/8 0/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2200
0690 0698 06A0 06A8 06B0 06B8 06B9
addq.l #1,* - - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2200
5290 5298 52A0 52A8 52B0 52B8 52B9
addx.l *,* - *124
-2/4
RI5
2208
D388
and.l *,d0 - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
C090 C098 C0A0 C0A8 C0B0 C0B8 C0B9
and.l d0,* *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
C190 C198 C1A0 C1A8 C1B0 C1B8 C1B9
and.l #1,* - *132 *132 *132 *136 *140 *136 *132
0/6 0/6 -4/6 2/6 6/6 0/8 0/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2208 2200
0290 0298 02A0 02A8 02B0 02B8 02B9
clr.l * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
4290 4298 42A0 42A8 42B0 42B8 42B9
cmp.l *,d0 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
B090 B098 B0A0 B0A8 B0B0 B0B8 B0B9
cmpa.l *,a1 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
B3D0 B3D8 B3E0 B3E8 B3F0 B3F8 B3F9
cmp.l #1,* - *132 *132 *132 *136 *140 *136 *132
0/6 0/6 -4/6 2/6 6/6 0/8 0/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2208 2200
0C90 0C98 0CA0 0CA8 0CB0 0CB8 0CB9
cmpm.l (a0)+,(a1)+ *124
0/4
RI5
2208
B388
eor.l d0,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
B190 B198 B1A0 B1A8 B1B0 B1B8 B1B9
eor.l #1,* - *132 *132 *132 *136 *140 *136 *136
0/6 0/6 -4/6 2/6 6/6 0/8 0/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2200 2208
0A90 0A98 0AA0 0AA8 0AB0 0AB8 0AB9
move.l *,d0 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
2010 2018 2020 2028 2030 2038 2039
move.l *,a1 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
2250 2258 2260 2268 2270 2278 2279
move.l *,(a1) - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
2290 2298 22A0 22A8 22B0 22B8 22B9
move.l *,(a1)+ - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
22D0 22D8 22E0 22E8 22F0 22F8 22F9
move.l *,-(a1) - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
2310 2318 2320 2328 2330 2338 2339
move.l *,2(a1) - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
2350 2358 2360 2368 2370 2378 2379
move.l *,2(a1,d0) - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
2390 2398 23A0 23A8 23B0 23B8 23B9
move.l *,W - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2200
21D0 21D8 21E0 21E8 21F0 21F8 21F9
move.l *,L - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2200
23D0 23D8 23E0 23E8 23F0 23F8 23F9
movem.l *,d0-d3 *128 *128 *132 *136 *132 *136 - -
0/6 0/6 2/8 6/8 0/8 0/A
RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200
4CD0 4CD8 4CE8 4CF0 4CF8 4CF9
movem.l d0-d3,* *128 *128 *132 *136 *132 *136
0/6 -2/6 2/8 6/8 0/8 0/A
WI5 WI5 WI5 WI5 WI5 WI5
2200 2208 2208 2200 2208 2200
48D0 48E0 48E8 48F0 48F8 48F9
movep.l d0,4(a1) -
movep.l 4(a0),d0 *128
4/2
RI5
2208
0148
neg.l * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
4490 4498 44A0 44A8 44B0 44B8 44B9
negx.l * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
4090 4098 40A0 40A8 40B0 40B8 40B9
not.l * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
4690 4698 46A0 46A8 46B0 46B8 46B9
or.l *,d0 - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
8090 8098 80A0 80A8 80B0 80B8 80B9
or.l d0,* *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
8190 8198 81A0 81A8 81B0 81B8 81B9
or.l #1,* - *132 *132 *132 *136 *140 *136 *128
0/6 0/6 -4/6 2/6 6/6 0/8 0/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2208 2200
0090 0098 00A0 00A8 00B0 00B8 00B9
sub.l *,d0 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2200 2208 2200 2208 2208
9090 9098 90A0 90A8 90B0 90B8 90B9
sub.l d0,* *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
9190 9198 91A0 91A8 91B0 91B8 91B9
suba.l *,a1 - - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2208 2200 2208 2200
93D0 93D8 93E0 93E8 93F0 93F8 93F9
sub.l #1,* - *132 *132 *132 *136 *140 *136 *136
0/6 0/6 -4/6 2/6 6/6 0/8 0/A
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2200 2208 2200 2200 2208 2208
0490 0498 04A0 04A8 04B0 04B8 04B9
subq.l #1,* - - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2200 2208 2200 2208
5390 5398 53A0 53A8 53B0 53B8 53B9
subx.l *,* - *124
-2/4
RI5
2200
9388
tst.l * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -4/2 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
4A90 4A98 4AA0 4AA8 4AB0 4AB8 4AB9
asl.w #1,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
E1D0 E1D8 E1E0 E1E8 E1F0 E1F8 E1F9
asr.w #1,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
E0D0 E0D8 E0E0 E0E8 E0F0 E0F8 E0F9
lsl.w #1,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
E3D0 E3D8 E3E0 E3E8 E3F0 E3F8 E3F9
lsr.w #1,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2200 2208 2200 2208 2208 2200
E2D0 E2D8 E2E0 E2E8 E2F0 E2F8 E2F9
rol.w #1,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
E7D0 E7D8 E7E0 E7E8 E7F0 E7F8 E7F9
ror.w #1,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
E6D0 E6D8 E6E0 E6E8 E6F0 E6F8 E6F9
roxl.w #1,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
E5D0 E5D8 E5E0 E5E8 E5F0 E5F8 E5F9
roxr.w #1,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
E4D0 E4D8 E4E0 E4E8 E4F0 E4F8 E4F9
bchg #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -1/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
0850 0858 0860 0868 0870 0878 0879
bchg d0,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -1/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
0150 0158 0160 0168 0170 0178 0179
bset #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -1/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
08D0 08D8 08E0 08E8 08F0 08F8 08F9
bset d0,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -1/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
01D0 01D8 01E0 01E8 01F0 01F8 01F9
bclr #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -1/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
0890 0898 08A0 08A8 08B0 08B8 08B9
bclr d0,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -1/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
0190 0198 01A0 01A8 01B0 01B8 01B9
btst #1,* - *128 *128 *128 *132 *136 *132 *136
0/4 0/4 -1/6 2/4 6/4 0/6 0/8
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
0810 0818 0820 0828 0830 0838 0839
btst d0,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -1/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
0110 0118 0120 0128 0130 0138 0139
mulu *,d0 - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
C0D0 C0D8 C0E0 C0E8 C0F0 C0F8 C0F9
muls *,d0 - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2208 2208 2200 2208 2200 2200 2208
C1D0 C1D8 C1E0 C1E8 C1F0 C1F8 C1F9
abcd *,* - *124
-1/4
RI5
2208
C308
nbcd * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -1/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2200 2208 2208 2200 2208
4810 4818 4820 4828 4830 4838 4839
sbcd *,* - *124
-1/4
RI5
2200
8308
st * - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -1/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
50D0 50D8 50E0 50E8 50F0 50F8 50F9
tas * - *124 *124 *128 *128 *132 *128 *132
0/2 0/2 -1/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
4AD0 4AD8 4AE0 4AE8 4AF0 4AF8 4AF9
move.w sr,* - *124 *124 *124 *128 *132 *128 *132
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
40D0 40D8 40E0 40E8 40F0 40F8 40F9
move.w *,ccr - *124 *124 *124 *128 *132 *128 *132 - - -
0/2 0/2 -2/4 2/2 6/2 0/4 0/6
RI5 RI5 RI5 RI5 RI5 RI5 RI5
2200 2208 2208 2200 2208 2200 2200
44D0 44D8 44E0 44E8 44F0 44F8 44F9
Re: Program counter and exception
Code: Select all
BUS error late (A1)
add.w *,d0 - - - - - - - - - - - -
add.w d0,* - - - - - - -
adda.w *,a1 - - - - - - - - - - - -
add.w #1,* - - - - - - - -
addq.w #1,* - - - - - - - - -
addx.w *,* - *132
-2/4
RI5
2200
D348
and.w *,d0 - - - - - - - - - - -
and.w d0,* - - - - - - -
and.w #1,* - - - - - - - -
clr.w * - - - - - - - -
cmp.w *,d0 - - - - - - - - - - - -
cmpa.w *,a1 - - - - - - - - - - - -
cmp.w #1,* - - - - - - - -
cmpm.w (a0)+,(a1)+ *128
0/4
RI5
2200
B348
eor.w d0,* - - - - - - - -
eor.w #1,* - - - - - - - -
move.w *,d0 - - - - - - - - - - - -
move.w *,a1 - - - - - - - - - - - -
move.w *,(a1) *124 *124 *128 *128 *132 *132 *136 *132 *136 *132 *136 *128
0/4 0/4 0/4 0/4 0/4 0/6 0/6 0/6 0/8 0/6 0/6 0/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
3280 3288 3290 3298 32A0 32A8 32B0 32B8 32B9 32BA 32BB 32BC
move.w *,(a1)+ *124 *124 *128 *128 *132 *132 *136 *132 *136 *132 *136 *128
0/4 0/4 0/4 0/4 0/4 0/6 0/6 0/6 0/8 0/6 0/6 0/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
32C0 32C8 32D0 32D8 32E0 32E8 32F0 32F8 32F9 32FA 32FB 32FC
move.w *,-(a1) *128 *128 *132 *132 *136 *136 *140 *136 *140 *136 *140 *132
-2/4 -2/4 -2/4 -2/4 -2/4 -2/6 -2/6 -2/6 -2/8 -2/6 -2/6 -2/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71
move.w *,2(a1) *128 *128 *132 *132 *136 *136 *140 *136 *140 *136 *140 *132
2/4 2/4 2/4 2/4 2/4 2/6 2/6 2/6 2/8 2/6 2/6 2/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
3340 3348 3350 3358 3360 3368 3370 3378 3379 337A 337B 337C
move.w *,2(a1,d0) *132 *132 *136 *136 *140 *140 *140 *124 *84 *68 *48 *32
6/4 6/4 6/4 6/4 6/4 6/6 6/6 6/6 6/8 6/6 6/6 6/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
3380 3388 3390 3398 33A0 33A8 33B0 33B8 33B9 33BA 33BB 33BC
move.w *,W *32 *36 *36 *40 *40 *32 *24 *8 *496 *496 *500 *0
0/4 0/4 0/4 0/4 0/4 0/6 0/6 0/6 0/8 0/6 0/6 0/6
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
31C0 31C8 31D0 31D8 31E0 31E8 31F0 31F8 31F9 31FA 31FB 31FC
move.w *,L *8 *16 *24 *32 *44 *80 *124 *136 *140 *136 *140 *132
0/6 0/6 0/4 0/4 0/4 0/6 0/6 0/6 0/8 0/6 0/6 0/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2204 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
33C0 33C8 33D0 33D8 33E0 33E8 33F0 33F8 33F9 33FA 33FB 33FC
movem.w *,d0-d3 - - - - - - - -
movem.w d0-d3,* - - - - - -
movep.w d0,4(a1) *128
4/2
WI5
2200
0189
movep.w 4(a0),d0 -
neg.w * - - - - - - - -
negx.w * - - - - - - - -
not.w * - - - - - - - -
or.w *,d0 - - - - - - - - - - -
or.w d0,* - - - - - - -
or.w #1,* - - - - - - - -
sub.w *,d0 - - - - - - - - - - - -
sub.w d0,* - - - - - - -
suba.w *,a1 - - - - - - - - - - - -
sub.w #1,* - - - - - - - -
subq.w #1,* - - - - - - - - -
subx.w *,* - *132
-2/4
RI5
2200
9348
tst.w * - - - - - - - -
add.l *,d0 - - - - - - - - - - - -
add.l d0,* - - - - - - -
adda.l *,a1 - - - - - - - - - - - -
add.l #1,* - - - - - - - -
addq.l #1,* - - - - - - - - -
addx.l *,* - *136
-2/4
RI5
2208
D388
and.l *,d0 - - - - - - - - - - -
and.l d0,* - - - - - - -
and.l #1,* - - - - - - - -
clr.l * - - - - - - - -
cmp.l *,d0 - - - - - - - - - - - -
cmpa.l *,a1 - - - - - - - - - - - -
cmp.l #1,* - - - - - - - -
cmpm.l (a0)+,(a1)+ *132
0/4
RI5
2208
B388
eor.l d0,* - - - - - - - -
eor.l #1,* - - - - - - - -
move.l *,d0 - - - - - - - - - - - -
move.l *,a1 - - - - - - - - - - - -
move.l *,(a1) *124 *124 *132 *132 *136 *136 *140 *136 *140 *136 *140 *132
0/4 0/4 0/4 0/4 0/4 0/6 0/6 0/6 0/8 0/6 0/6 0/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2208 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
2280 2288 2290 2298 22A0 22A8 22B0 22B8 22B9 22BA 22BB 22BC
move.l *,(a1)+ *124 *124 *132 *132 *136 *136 *140 *136 *140 *136 *140 *132
0/4 0/4 0/4 0/4 0/4 0/6 0/6 0/6 0/8 0/6 0/6 0/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2208 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2208
22C0 22C8 22D0 22D8 22E0 22E8 22F0 22F8 22F9 22FA 22FB 22FC
move.l *,-(a1) *128 *128 *136 *136 *140 *140 *144 *140 *144 *140 *144 *136
-2/4 -2/4 -2/4 -2/4 -2/4 -2/6 -2/6 -2/6 -2/8 -2/6 -2/6 -2/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
2300 2308 2310 2318 2320 2328 2330 2338 2339 233A 233B 233C
move.l *,2(a1) *128 *128 *136 *136 *140 *140 *144 *140 *104 *88 *68 20
2/4 2/4 2/4 2/4 2/4 2/6 2/6 2/6 2/8 2/6 2/6 2/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
2340 2348 2350 2358 2360 2368 2370 2378 2379 237A 237B 237C
move.l *,2(a1,d0) *12 *16 16 *140 *144 *144 *148 *144 *148 *144 *128 *80
6/4 6/4 6/4 6/4 6/4 6/6 6/6 6/6 6/8 6/6 6/6 6/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
2380 2388 2390 2398 23A0 23A8 23B0 23B8 23B9 23BA 23BB 23BC
move.l *,W *72 *72 *76 *76 *68 *52 *32 *16 *496 *496 *508 *36
0/4 0/4 0/4 0/4 0/4 0/6 0/6 0/6 0/8 0/6 0/6 0/8
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
21C0 21C8 21D0 21D8 21E0 21E8 21F0 21F8 21F9 21FA 21FB 21FC
move.l *,L *40 *48 *60 *68 *80 *116 *144 *140 *144 *140 *108 *60
0/6 0/6 0/4 0/4 0/4 0/6 0/6 0/6 0/8 0/6 0/6 0/A
WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5 WI5
2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200 2200
23C0 23C8 23D0 23D8 23E0 23E8 23F0 23F8 23F9 23FA 23FB 23FC
movem.l *,d0-d3 - - - - - - - -
movem.l d0-d3,* - - - - - -
movep.l d0,4(a1) *128
4/2
WI5
2208
01C9
movep.l 4(a0),d0 -
neg.l * - - - - - - - -
negx.l * - - - - - - - -
not.l * - - - - - - - -
or.l *,d0 - - - - - - - - - - -
or.l d0,* - - - - - - -
or.l #1,* - - - - - - - -
sub.l *,d0 - - - - - - - - - - - -
sub.l d0,* - - - - - - -
suba.l *,a1 - - - - - - - - - - - -
sub.l #1,* - - - - - - - -
subq.l #1,* - - - - - - - - -
subx.l *,* - *136
-2/4
RI5
2208
9388
tst.l * - - - - - - - -
asl.w #1,* - - - - - - - -
asr.w #1,* - - - - - - - -
lsl.w #1,* - - - - - - - -
lsr.w #1,* - - - - - - - -
rol.w #1,* - - - - - - - -
ror.w #1,* - - - - - - - -
roxl.w #1,* - - - - - - - -
roxr.w #1,* - - - - - - - -
bchg #1,* - - - - - - - -
bchg d0,* - - - - - - - -
bset #1,* - - - - - - - -
bset d0,* - - - - - - - -
bclr #1,* - - - - - - - -
bclr d0,* - - - - - - - -
btst #1,* - - - - - - - -
btst d0,* - - - - - - - -
mulu *,d0 - - - - - - - - - - -
muls *,d0 - - - - - - - - - - -
abcd *,* - *132
-1/4
RI5
2208
C308
nbcd * - - - - - - - -
sbcd *,* - *132
-1/4
RI5
2200
8308
st * - - - - - - - -
tas * - - - - - - - -
move.w sr,* - - - - - - - -
move.w *,ccr - - - - - - - - - - -
Re: Program counter and exception
From looking at the data, I've failed to find a general theory that works, by the way.
I have one that works for a percentage of cases, but not all - some instructions (notably the movem case that scuppers Blood Money) clearly behave differently to a more general case that works for typical ALU instructions.
That's before even considering trying to get the offset and cycle count right at the same time
.
I have one that works for a percentage of cases, but not all - some instructions (notably the movem case that scuppers Blood Money) clearly behave differently to a more general case that works for typical ALU instructions.
That's before even considering trying to get the offset and cycle count right at the same time
.-
Steven Seagal
- Fuji Shaped Bastard
- Posts: 2018
- Joined: Sun Dec 04, 2005 9:12 am
- Location: Undisclosed
- Contact:
Re: Program counter and exception
For MOVEM I even wonder if prefetch really occurs at the end.
I'll look at your tables with interest.
I'll look at your tables with interest.
In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
-
Steven Seagal
- Fuji Shaped Bastard
- Posts: 2018
- Joined: Sun Dec 04, 2005 9:12 am
- Location: Undisclosed
- Contact:
Re: Program counter and exception
If we take the 1st case:
In my theory PC won't be incremented for prefetch before we've got <EA>.
For -(A) it's like the CPU makes 'PC+2' at the same time it makes A-1? I just don't get it.
I also don't get why PC isn't higher for $(A) and I(A): it should fetch operands before computing the address and then crash.
If those tables are exact, and I don't doubt they are, then the situation is chaotic and hacks based on opcode are the only sane solution.
Code: Select all
Name : Dn An (A) (A)+ -(A) $(A) I(A) .W .L $(P) I(P) #
ADDRESS error early (A0)
add.w *,d0 - - *56 *56 *60 *60 *64 *60 *64 *60 *64 -
1/2 1/2 -1/4 3/2 7/2 1/4 1/6 7/2 B/2
RI5 RI5 RI5 RI5 RI5 RI5 RI5 RI6 RI6
2208 2208 2200 2208 2200 2200 2208 2200 2208
D050 D058 D060 D068 D070 D078 D079 D07A D07B
In my theory PC won't be incremented for prefetch before we've got <EA>.
For -(A) it's like the CPU makes 'PC+2' at the same time it makes A-1? I just don't get it.
I also don't get why PC isn't higher for $(A) and I(A): it should fetch operands before computing the address and then crash.
If those tables are exact, and I don't doubt they are, then the situation is chaotic and hacks based on opcode are the only sane solution.
In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
Re: Program counter and exception
Yes. That was one of the empyrical rules I inferred: extra fetches for absolute addressing and predecrement are visible on BE/AE, but displacement or indexed ones aren't - even though, in both cases, all the fetches appear to have been issued (which can be inferred from the cycle count - $(A) is the same size as X.W, both with 60 cycles and I(A) or I(PC) is the same size as X.L, both with 64).
I think I see three different cases, but two of them may be degenerate:
- offset, indexed (A-register or PC-relative) require an ALU computation of the form (reg + some stuff) in a temp register, which is then discarded
- Predecrement puts the actual A register onto the bus (because the predec occurs before the bus cycle starts).
- absolute requires prefetch reads into a temp area, which is then discarded. But this is probably the same as the previous case, if the two values waiting in the prefetch registers are simply considered a 32-bit value and put on the bus.
Exactly why the second cases cause the 'post prefetch' PC to be visible, but the former don't, I don't know. If it was the other way round it would be more intutive, since the latter case actually has all the information it needs at the start of the instruction and could do the prefetches later. But then the cycle count wouldn't match up for late prefetch.
ijor and I had a brief discussion about it a few years ago when I generated the tables, as I (mis?)understood his view it was largely not to try to work it out but just accept it and make it work, while I still prefer looking for the logic behind it in order to try to do something that isn't just table-driven or a reverse-engineered hack. But maybe it's not possible (I'm not at all sure it is in the general case).
I think I see three different cases, but two of them may be degenerate:
- offset, indexed (A-register or PC-relative) require an ALU computation of the form (reg + some stuff) in a temp register, which is then discarded
- Predecrement puts the actual A register onto the bus (because the predec occurs before the bus cycle starts).
- absolute requires prefetch reads into a temp area, which is then discarded. But this is probably the same as the previous case, if the two values waiting in the prefetch registers are simply considered a 32-bit value and put on the bus.
Exactly why the second cases cause the 'post prefetch' PC to be visible, but the former don't, I don't know. If it was the other way round it would be more intutive, since the latter case actually has all the information it needs at the start of the instruction and could do the prefetches later. But then the cycle count wouldn't match up for late prefetch.
ijor and I had a brief discussion about it a few years ago when I generated the tables, as I (mis?)understood his view it was largely not to try to work it out but just accept it and make it work, while I still prefer looking for the logic behind it in order to try to do something that isn't just table-driven or a reverse-engineered hack. But maybe it's not possible (I'm not at all sure it is in the general case).
Re: Program counter and exception
This is the key statement:
I presumed something like this existed for either computing the prefetch address or computing the address to stack on call/exception (since one or the other must require an ALU operation). The former might make more sense, since the latter would require two ALU ops per fetch (one to compute the address, another to increment the PC) although it may have enough time for that since a fetch is 4 cycles. I would guess this ALU is a simple adder whose first input is 23 bits (assumed bit zero 0) and the second is a few small values (e.g. -2, 2, 4), so most of the stages are just cheap carry propagation.
It looks like in some cases the prefetch happens with the new PC and written back to the actual PC register, while in some it is not.
The microcode will probably explain all this fairly thoroughly, so roll on the project to get a human-readable version of it.
"A limited arithmetic unit is located in the HIGH and LOW sections, and a general capability arithmetic and logical unit is located in the DATA section. This allows address and data calculations to occur simultaneously. For example, it is possible to do a register-to-register word addition concurrently with a program counter increment".
I presumed something like this existed for either computing the prefetch address or computing the address to stack on call/exception (since one or the other must require an ALU operation). The former might make more sense, since the latter would require two ALU ops per fetch (one to compute the address, another to increment the PC) although it may have enough time for that since a fetch is 4 cycles. I would guess this ALU is a simple adder whose first input is 23 bits (assumed bit zero 0) and the second is a few small values (e.g. -2, 2, 4), so most of the stages are just cheap carry propagation.
It looks like in some cases the prefetch happens with the new PC and written back to the actual PC register, while in some it is not.
The microcode will probably explain all this fairly thoroughly, so roll on the project to get a human-readable version of it.
Re: Program counter and exception
Here's a pair of wild guesses, based on the fact that the ones that don't increment are using the ALU during the prefetch(es) - to do the more complex displacement+reg or displacement+reg+reg operation - while the ones that do increment PC with each fetch don't.
1. With the ALU busy, there is no writeback path available from the address generation unit for the PC register to be updated, so it isn't, and then later on it is updated on a cycle where the register write path is idle. In contrast, in the absolute and predecrement cases, since the ALU is idle during the prefetch the PC can be written back from the address generation unit as the fetch proceeds. So the 'starvation' is of the register write path, which may only be able to write one register per cycle (or maybe even 2 clock cycles).
2. There is actually no writeback path at all from the AGU. The address generation for prefetch is entirely performed in the address generation unit, and the PC value really is the current PC. So the address generation unit generates 'PC+N' for each prefetch. The actual PC increment is performed in the ALU during a cycle where it isn't otherwise busy.
If either is the case, it would not be impossible to model this in the emulator, although it's going to be a bit complicated. And there are still clearly cases like movem which don't follow this precisely.
1. With the ALU busy, there is no writeback path available from the address generation unit for the PC register to be updated, so it isn't, and then later on it is updated on a cycle where the register write path is idle. In contrast, in the absolute and predecrement cases, since the ALU is idle during the prefetch the PC can be written back from the address generation unit as the fetch proceeds. So the 'starvation' is of the register write path, which may only be able to write one register per cycle (or maybe even 2 clock cycles).
2. There is actually no writeback path at all from the AGU. The address generation for prefetch is entirely performed in the address generation unit, and the PC value really is the current PC. So the address generation unit generates 'PC+N' for each prefetch. The actual PC increment is performed in the ALU during a cycle where it isn't otherwise busy.
If either is the case, it would not be impossible to model this in the emulator, although it's going to be a bit complicated. And there are still clearly cases like movem which don't follow this precisely.
Re: Program counter and exception
Interesting facts about AUs that I can remember :
they have 6 operations : +1, +2, +4 and -1, -2, -4
they act as an internal register between two nanoword executions.
most of the time (always ?), between two intruction executions, au=pc+2.
Yes, I think I have almost everything necessary to write such a table (minus time, perhaps).
I have to release my version of the "corrected" transcript of motorola patents as it can be a real good start.
they have 6 operations : +1, +2, +4 and -1, -2, -4
they act as an internal register between two nanoword executions.
most of the time (always ?), between two intruction executions, au=pc+2.
Dio wrote:The microcode will probably explain all this fairly thoroughly, so roll on the project to get a human-readable version of it.
Yes, I think I have almost everything necessary to write such a table (minus time, perhaps).
I have to release my version of the "corrected" transcript of motorola patents as it can be a real good start.
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Re: Program counter and exception
danorf wrote:Interesting facts about AUs that I can remember :
they have 6 operations : +1, +2, +4 and -1, -2, -4
Certainly thought they did more, like indexing (D16+An etc.)
In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
Re: Program counter and exception
That would be expensive - a full (24-bit!) adder costs a lot more than a simple +(1/2/4), and it can be done in the ALU since there's plenty of time during the prefetches. The more I think about it, the more I'm sure doing PC+N writeback in the ALU is the main reason for the BE / AE PC stacking.
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Re: Program counter and exception
Hey I looked at the microcodes for ADD -(An),D0 and here are some partial insights:
- All 'get <EA>' parts use the same routines in all instructions, so it's not that horrible.
- At the end of an instruction, AU = PC+2 (haven't checked all!).
- For EA=-(An), there is a strange AU->PC as first move of the routine, which explains value of PC. Note that it isn't prefetch.
This confirms the table for this case.
So in my theory I would add:
"if there's a crash during 'get <EA>' and it's -(An), we make 'PC+2'."
- All 'get <EA>' parts use the same routines in all instructions, so it's not that horrible.
- At the end of an instruction, AU = PC+2 (haven't checked all!).
- For EA=-(An), there is a strange AU->PC as first move of the routine, which explains value of PC. Note that it isn't prefetch.
This confirms the table for this case.
So in my theory I would add:
"if there's a crash during 'get <EA>' and it's -(An), we make 'PC+2'."
In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
Re: Program counter and exception
Anything interesting for abs.L and abs.W?
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Steven Seagal
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Re: Program counter and exception
Gimme some time!
In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
Re: Program counter and exception
Note that I doubt all instructions use exactly the same EA access rules. movem is one example, and another is move.w d0,* - it looks like the EA setup for the destination address always sees the clock cycles of the fetches for the destination EA calculation, whatever the addressing mode is. This is different to add d0,* for example. I imagine that these are relatively rare though.
I'll see if I can get the tester into a form you can run and generate the tables yourself for your version of STeem, so you can compare with the golds. No promise on the timescale for this though.
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Steven Seagal
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Re: Program counter and exception
Yes I meant instructions using EA (including MOVE).
MOVEM is different. I must still find it in the patent, maybe other names, and so maybe the microcode schemas aren't correct anyway for this one.
All I could do, but that's already much, is confirm the situation for <EA>.
Note that it implies that it is the PC register itself that is pushed on the exception stack frame.
The ? mean I didn't really check yet...
How is it possible? At first sight it makes no sense but when you read the microcode, you understand that it uses all sort of internal registers, and 'AU'.
The second instruction routine (after <EA>) makes PC=AU, so the value of PC at the end of <EA> doesn't matter for the CPU: this explains the mystery.
To me, that means that we can still develop a general rule, with maybe specific 'PC+2' correctly placed in the rest of instruction, but it will take some time. I already started updating my theory, I'll certainly post updates.
You leave me all the fun good sports!
MOVEM is different. I must still find it in the patent, maybe other names, and so maybe the microcode schemas aren't correct anyway for this one.
All I could do, but that's already much, is confirm the situation for <EA>.
Code: Select all
.B, .W .L
Dn PC(?) PC(?)
An PC(?) PC(?)
(An) PC PC(?)
(An)+ PC PC(?)
–(An) PC+2 PC
(d16, An) PC PC(?)
(d8, An, Xn) PC PC(?)
(xxx).W PC+2 PC+2(?)
(xxx).L PC+4 PC+4(?)
(d16, PC) PC PC(?)
(d8, PC, Xn) PC PC(?)
#<data> PC+2 PC+4
Note that it implies that it is the PC register itself that is pushed on the exception stack frame.
The ? mean I didn't really check yet...
How is it possible? At first sight it makes no sense but when you read the microcode, you understand that it uses all sort of internal registers, and 'AU'.
The second instruction routine (after <EA>) makes PC=AU, so the value of PC at the end of <EA> doesn't matter for the CPU: this explains the mystery.
To me, that means that we can still develop a general rule, with maybe specific 'PC+2' correctly placed in the rest of instruction, but it will take some time. I already started updating my theory, I'll certainly post updates.
You leave me all the fun good sports!
In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
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Steven Seagal
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Re: Program counter and exception
This version reflects what I (think I) know today, it's incomplete but not speculative anymore.
Program counter and exception
Scope
This text doesn't describe the full exception process on the M68000 nor even
how the full exception stack frame is built.
You need to check other doc for those aspects.
It is also useful to check doc on prefetch.
The text only focuses on the exact value of the program counter (PC) that is
pushed on the stack when an address or bus error exception occurs.
Sources
- Motorola M68000 Microprocessors User's Manual (www.freescale.com)
- US patent 4,325,121 assigned to Motorola
- Discussions in Atari-Forum (www.atari-forum.com)
- Exception PC tables by 'Dio' (Atari-Forum)
- wikipedia.org and maybe other web sites
- And of course development of Steem SSE: for this reason, Steem specifics are
discussed.
Caveat
This 2nd version of the text is based on more actual data and less guessing!
Nonetheless, the 'microcodes' aspects must still be studied a bit more.
Why?
This aspect of ST emulation came to attention when it was realised that some
programs work or crash based on that value being correct, mainly in the context
of code protection.
For example, the value pushed on a (very) low stack would later be executed as
code, which is a rather intricate procedure.
If the value is wrong, the instruction is garbage.
Cases
Need an adjustment:
Blood Money (+2)
Phaleon, European Demos, Transbeauce 2 (-2) (*)
War Heli (+2)
(*) Don't know why but those demos also work without adjustment in the current
build of Steem SSE. This wasn't the case before.
Need no adjustment (or it crashes!)
BIG demo
Darkside of the Spoon
(...) many!
Tables
Dio from Atari-Forum wrote a test program that issued tables for a lot
of cases (also available here: Exception PC tables.txt).
The only value of interest for us is PC (2nd value after the / on
line 2, values are relative to PC of current instruction, but normally
PC is already 2 bytes beyond (so 2 in the table means no increment yet
at time of crash).
Up to now those tables have been confirmed by known cases and microcode
analysis (see below), so we take them to be solid.
User Manual
The M68000 User's Manual states:
"Value saved for the program counter is advanced 2–10 bytes beyond the address
of the first word of the instruction that made the reference causing the bus
error.
If the bus error occurred during the fetch of the next instruction, the saved
program counter has a value in the vicinity of the current instruction, even
if the current instruction is a branch, a jump, or a return instruction."
Based on just that, the programmer who would actually use the pushed PC
couldn't compute it. He had to be lucky or to test on real hardware.
Program Counter
There is only one PC register in the M68000. When a crash occurs, the exact
content of the register at that time is copied, not some fancy value. So this
is the register that counts in our context.
Fetching
The PC (program counter) points to a word (16bit value) in memory that is
supposed to be fetched. A fetch is copying the value pointed by PC to a
register in the CPU (IRC). Those values are the program, made of macro-
instructions, that is instructions and their operands.
Both the instructions and the operands are fetched but only the instructions
are decoded (going from register IRC to register IRD where decoding is done).
Increment time
When a word is fetched, PC is incremented (PC=PC+2, shortened as 'PC+2') to
point to the correct word.
The first question is: do we increment then fetch, or fetch then increment?
It depends on the processor:
"In most processors, PC is incremented after fetching an instruction,
and holds the memory address of (“points to”) the next instruction that
would be executed. (In a processor where the incrementation precedes the
fetch, PC points to the current instruction being executed.) "
(http://en.wikipedia.org/wiki/Program_counter)
On the M68000, when an instruction starts, PC points to the next word.
So apparently it would be 'fetch then increment'.
But in fact, it points to the word being currently copied in IRC (prefetch
rule: at the start of any instruction, IRC is loaded with the next instruction
or operand).
It implies that the PC isn't incremented right after the word in memory
has been fetched. After fetching, PC points to the last word having been
fetched.
Separation of incrementing and fetching
The second question is: does the fetch immediately follow PC increment, or coud
there be some delay between both events?
In the first case, the CPU would use one unique routine to fetch program words.
In the second case, at least two routines would be used to accomplish those
tasks.
Both possibilities makes sense. On the M68000, the second possibility is true:
increment and fetching are separate.
Microcode and Internal registers
All M68000 behaviour is commanded by microcodes, sort of mini-instructions
(and actually called 'micro' and 'nano' instructions by Motorola) or routines.
This applies to 'PC+2' and fetching as well.
There are also other internal registers in the CPU invisible to the programmer.
Those registers are involved in fetching, it's not just PC and IRC, for any
reasons (performance for example).
What's more, the address currently stored in the AU (double 16bit Arithmetic
Unit) is heavily used.
This has many consequences but the one that interests us here is that the
value of PC will always point to the word that's in IRC at the end of the
instruction, but there's no guarantee at all that the PC register is up to
date while the instruction isn't finished.
Hacks are legit
Since each instruction is uniquely commanded by microcodes, adjusting the PC
for specific instructions (based on opcode) is legit.
Real emulation
One could endeavour to emulate the CPU at microcode and internal register
level.
Steem: in between
In Steem SSE, the way chosen is that there's no PC adjustment at the time we
must build the exception stack frame, we see to it that the value of PC
(variable pc) is correct in case of a bus or address error. So we adjust PC
as necessary in various phases of the instruction. But we don't emulate AU nor
the more obscure internal registers (yet!)
To do that, we use the microcodes and the Exception PC table.
This work may be progressive without breaking anything.
Effective Address
On the M68000, a generic microcode routine is used to read the effective
address when the instruction needs it (most instructions including MOVE).
This implies that prefetch can't happen before or during getting effective
address.
That there be no prefetch doesn't mean that PC is unchanged. First, of course,
PC may be updated when operands are fetched.
Second, microcode may update PC as part of the <EA> routine.
Note that <EA> is called also for instructions that shouldn't need to read
the value, it's a simplification in the CPU design. That means that most
crashes will happen here, only MOVE and MOVEM (and...?) directly write on an
address without reading.
Analysis of microcodes delivers the following table:
[some values still to be confirmed! but I think they will be]
The values may look strange to the M68000 expert, but they are explained
above by the use of other registers than PC, while only PC is pushed on
the stack.
[TODO find the exception microcodes that do it]
In fact, it seems that the first step of the routine executed after <EA> is
'PC=AU'.
[TODO the rest!]
[Already done: the cases that handle
Blood Money: movem.l a0-5,(a6)
War Heli: move.l d5,(a1)
based on the tables, not the microcodes]
Edit: made it more readable as a post
Program counter and exception
Scope
This text doesn't describe the full exception process on the M68000 nor even
how the full exception stack frame is built.
You need to check other doc for those aspects.
It is also useful to check doc on prefetch.
The text only focuses on the exact value of the program counter (PC) that is
pushed on the stack when an address or bus error exception occurs.
Sources
- Motorola M68000 Microprocessors User's Manual (www.freescale.com)
- US patent 4,325,121 assigned to Motorola
- Discussions in Atari-Forum (www.atari-forum.com)
- Exception PC tables by 'Dio' (Atari-Forum)
- wikipedia.org and maybe other web sites
- And of course development of Steem SSE: for this reason, Steem specifics are
discussed.
Caveat
This 2nd version of the text is based on more actual data and less guessing!
Nonetheless, the 'microcodes' aspects must still be studied a bit more.
Why?
This aspect of ST emulation came to attention when it was realised that some
programs work or crash based on that value being correct, mainly in the context
of code protection.
For example, the value pushed on a (very) low stack would later be executed as
code, which is a rather intricate procedure.
If the value is wrong, the instruction is garbage.
Cases
Need an adjustment:
Blood Money (+2)
Phaleon, European Demos, Transbeauce 2 (-2) (*)
War Heli (+2)
(*) Don't know why but those demos also work without adjustment in the current
build of Steem SSE. This wasn't the case before.
Need no adjustment (or it crashes!)
BIG demo
Darkside of the Spoon
(...) many!
Tables
Dio from Atari-Forum wrote a test program that issued tables for a lot
of cases (also available here: Exception PC tables.txt).
The only value of interest for us is PC (2nd value after the / on
line 2, values are relative to PC of current instruction, but normally
PC is already 2 bytes beyond (so 2 in the table means no increment yet
at time of crash).
Up to now those tables have been confirmed by known cases and microcode
analysis (see below), so we take them to be solid.
User Manual
The M68000 User's Manual states:
"Value saved for the program counter is advanced 2–10 bytes beyond the address
of the first word of the instruction that made the reference causing the bus
error.
If the bus error occurred during the fetch of the next instruction, the saved
program counter has a value in the vicinity of the current instruction, even
if the current instruction is a branch, a jump, or a return instruction."
Based on just that, the programmer who would actually use the pushed PC
couldn't compute it. He had to be lucky or to test on real hardware.
Program Counter
There is only one PC register in the M68000. When a crash occurs, the exact
content of the register at that time is copied, not some fancy value. So this
is the register that counts in our context.
Fetching
The PC (program counter) points to a word (16bit value) in memory that is
supposed to be fetched. A fetch is copying the value pointed by PC to a
register in the CPU (IRC). Those values are the program, made of macro-
instructions, that is instructions and their operands.
Both the instructions and the operands are fetched but only the instructions
are decoded (going from register IRC to register IRD where decoding is done).
Increment time
When a word is fetched, PC is incremented (PC=PC+2, shortened as 'PC+2') to
point to the correct word.
The first question is: do we increment then fetch, or fetch then increment?
It depends on the processor:
"In most processors, PC is incremented after fetching an instruction,
and holds the memory address of (“points to”) the next instruction that
would be executed. (In a processor where the incrementation precedes the
fetch, PC points to the current instruction being executed.) "
(http://en.wikipedia.org/wiki/Program_counter)
On the M68000, when an instruction starts, PC points to the next word.
So apparently it would be 'fetch then increment'.
But in fact, it points to the word being currently copied in IRC (prefetch
rule: at the start of any instruction, IRC is loaded with the next instruction
or operand).
It implies that the PC isn't incremented right after the word in memory
has been fetched. After fetching, PC points to the last word having been
fetched.
Separation of incrementing and fetching
The second question is: does the fetch immediately follow PC increment, or coud
there be some delay between both events?
In the first case, the CPU would use one unique routine to fetch program words.
In the second case, at least two routines would be used to accomplish those
tasks.
Both possibilities makes sense. On the M68000, the second possibility is true:
increment and fetching are separate.
Microcode and Internal registers
All M68000 behaviour is commanded by microcodes, sort of mini-instructions
(and actually called 'micro' and 'nano' instructions by Motorola) or routines.
This applies to 'PC+2' and fetching as well.
There are also other internal registers in the CPU invisible to the programmer.
Those registers are involved in fetching, it's not just PC and IRC, for any
reasons (performance for example).
What's more, the address currently stored in the AU (double 16bit Arithmetic
Unit) is heavily used.
This has many consequences but the one that interests us here is that the
value of PC will always point to the word that's in IRC at the end of the
instruction, but there's no guarantee at all that the PC register is up to
date while the instruction isn't finished.
Hacks are legit
Since each instruction is uniquely commanded by microcodes, adjusting the PC
for specific instructions (based on opcode) is legit.
Real emulation
One could endeavour to emulate the CPU at microcode and internal register
level.
Steem: in between
In Steem SSE, the way chosen is that there's no PC adjustment at the time we
must build the exception stack frame, we see to it that the value of PC
(variable pc) is correct in case of a bus or address error. So we adjust PC
as necessary in various phases of the instruction. But we don't emulate AU nor
the more obscure internal registers (yet!)
To do that, we use the microcodes and the Exception PC table.
This work may be progressive without breaking anything.
Effective Address
On the M68000, a generic microcode routine is used to read the effective
address when the instruction needs it (most instructions including MOVE).
This implies that prefetch can't happen before or during getting effective
address.
That there be no prefetch doesn't mean that PC is unchanged. First, of course,
PC may be updated when operands are fetched.
Second, microcode may update PC as part of the <EA> routine.
Note that <EA> is called also for instructions that shouldn't need to read
the value, it's a simplification in the CPU design. That means that most
crashes will happen here, only MOVE and MOVEM (and...?) directly write on an
address without reading.
Analysis of microcodes delivers the following table:
[some values still to be confirmed! but I think they will be]
Code: Select all
b543 b210 Mode .B, .W .L
000 R Dn PC PC
001 R An PC PC
010 R (An) PC PC
011 R (An)+ PC PC
100 R –(An) PC+2 PC
101 R (d16, An) PC PC
110 R (d8, An, Xn) PC PC
111 000 (xxx).W PC+2 PC+2
111 001 (xxx).L PC+4 PC+4
111 010 (d16, PC) PC PC
111 011 (d8, PC, Xn) PC PC
111 100 #<data> PC+2 PC+4
The values may look strange to the M68000 expert, but they are explained
above by the use of other registers than PC, while only PC is pushed on
the stack.
[TODO find the exception microcodes that do it]
In fact, it seems that the first step of the routine executed after <EA> is
'PC=AU'.
[TODO the rest!]
[Already done: the cases that handle
Blood Money: movem.l a0-5,(a6)
War Heli: move.l d5,(a1)
based on the tables, not the microcodes]
Edit: made it more readable as a post
Last edited by Steven Seagal on Sun Mar 31, 2013 8:20 am, edited 1 time in total.
In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
Re: Program counter and exception
Steven Seagal wrote:
Certainly thought they did more, like indexing (D16+An etc.)
I confirm what Dio says : all effective adress calculation are done by the ALU and not by the AUs.
AUs are only used to calculate address of the next word to prefetch and PC value.
Making a table to know what is the exact value of PC in case of bus or adress error during every instruction is interesting and can surely be done and I can help you to write it if you really want.
But I think it's time to think differently. If continuing with tables, you'll need a table for pairing, a table for prefetch, a table for accurate pc value, ...
Perhaps it's beter to think of emulating micro/nanowords for each clock cycles. It will skip the need of all these tables...
Steven Seagal wrote:Hey I looked at the microcodes for ADD -(An),D0 and here are some partial insights:
- All 'get <EA>' parts use the same routines in all instructions, so it's not that horrible.
- At the end of an instruction, AU = PC+2 (haven't checked all!).
- For EA=-(An), there is a strange AU->PC as first move of the routine, which explains value of PC. Note that it isn't prefetch.
This confirms the table for this case.
So in my theory I would add:
"if there's a crash during 'get <EA>' and it's -(An), we make 'PC+2'."
The <EA> calculation routs are the easy part (some intructions will be really hard to trace and provides many ways of having an address error or a bus error).
You're right for -(An) case (PC+2 form start) (and it's the same for (d16,An)) but only for .w instructons (it's different with .l) (AU value is a little more complex to find).
For oter <EA> calculation it's not so simple and PC and AU will not be the same if the instruction is interreupted by an address error or a bus error.
Re: Program counter and exception
Dio wrote::D
Note that I doubt all instructions use exactly the same EA access rules. movem is one example, and another is move.w d0,* - it looks like the EA setup for the destination address always sees the clock cycles of the fetches for the destination EA calculation, whatever the addressing mode is. This is different to add d0,* for example. I imagine that these are relatively rare though.
You can use the table posted here : http://www.atari-forum.com/viewtopic.php?f=68&t=24710 to see what instruction use the general <EA> calculation routs and which instruction does not.
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Re: Program counter and exception
danorf wrote:The <EA> calculation routs are the easy part (some intructions will be really hard to trace and provides many ways of having an address error or a bus error).
We may work progressively, first working on the cases we know.
You're right for -(An) case (PC+2 form start) (and it's the same for (d16,An)) but only for .w instructons (it's different with .l) (AU value is a little more complex to find).
For oter <EA> calculation it's not so simple and PC and AU will not be the same if the instruction is interreupted by an address error or a bus error.
I haven't seen it for (d16,An), my current table is (as posted right above in "code" precisely because of the table):
Code: Select all
b543 b210 Mode .B, .W .L
000 R Dn PC PC
001 R An PC PC
010 R (An) PC PC
011 R (An)+ PC PC
100 R –(An) PC+2 PC
101 R (d16, An) PC PC
110 R (d8, An, Xn) PC PC
111 000 (xxx).W PC+2 PC+2
111 001 (xxx).L PC+4 PC+4
111 010 (d16, PC) PC PC
111 011 (d8, PC, Xn) PC PC
111 100 #<data> PC+2 PC+4
But I haven't checked all microcodes for .L yet.
I have some questions when you have time, trying to validate my theories:
Do you agree that for B/A exceptions, PC is pushed and not, say, AU or a computed value?
Is it right that all instructions that use <EA> routine also make 'PC=AU' as first step of their proper routine, so that AU counts, not PC, for the CPU at the end of <EA>?
For MOVEM, are the microcodes called STM... and LDM...? It seems there are conflicting names in the patent.
For MOVEM to Memory, does prefetch occur before writing to memory?
Are there microcodes for exceptions? What would be the name for 'bus error'?
When the CPU needs the value in IRC, it may in fact read an intermediary register instead? (like 'dbin')
And when the CPU takes that IRC value (takes no read cycles), it fetches at once to fill it again, so that our timings are right?
(sorry for all the questions!
)In the CIA we learned that ST ruled
Steem SSE: http://sourceforge.net/projects/steemsse
Steem SSE: http://sourceforge.net/projects/steemsse
Re: Program counter and exception
Steven Seagal wrote:Do you agree that for B/A exceptions, PC is pushed and not, say, AU or a computed value?
Here i how stack frame is written when Bus or Address error occurs :
Start at microword bser1 (bser is for BuS ERror -address bus or data bus-) and following nanowords bser1, bser2, bser3, bser4, bser5, bser6, trap3, trap4, trap5, ... (trap is for trap
so address and data bus errors have common nanowords with traps). In the following I only repport things that are about writing the stack frame, so it's far from the complete processing of exception.In code section that follows :
pcl = pc lower 16bits
pch = pc higher 16bits
at = temporary address register
atl = at lower 16bits
ath = at higher 16bits
au, at, pc, sp ar 32bit registers
alu, ftu are 16bit registers
ird = instruction register decoder
psw = program status word
ssw = special word which monitors status of current instruction
Code: Select all
at= address curently on the address bus
bser1 au = pc
ftu = psw
bser2 alu = au = pcl
au = sp-2
write alu at au <--> write pcl at sp-2
bser3 alu = ftu = psw
au = sp-6
write alu at au <--> write psw at sp-6
bser4 alu = pch
ftu = ird
au = sp-4
write alu at au <--> write pch at sp-4
bser5 alu = ftu = ird
au = sp-8
write alu at au <--> write ird at sp-8
alu = atl = address on the address bus when error occurs
bser6 pc = at = address on the address bus when error occurs
ftu = ssw
au = sp-10
write alu at au <--> write atl at sp-10
trap3 alu = ftu = ssw
au = au-4 = sp-14
write alu at au and sp=au <--> write ssw at sp-14
trap4 sp = sp-14
alu = pch = ath
au = au+2 = old_sp-12 = new_sp+2
trap5 write alu at au <--> write ath at old_sp-12 (new_sp+2)
...
...
...
... ...
...Steven Seagal wrote:Is it right that all instructions that use <EA> routine also make 'PC=AU' as first step of their proper routine, so that AU counts, not PC, for the CPU at the end of <EA>?
Not sure to understand well the question, but you have to think of PC as "an exernal register" and of AU as "an internal register". When executing micro/nanowords, the CPU mostly always rely on AU. AU is set regarding of PC at the start of the operation and PC is corrected somewhere in the process.
Steven Seagal wrote:For MOVEM, are the microcodes called STM... and LDM...? It seems there are conflicting names in the patent.
I don't remember if there were conflicts in the original patent, but there's not in the transcript I have !
LDM... is for LoaD from Memory
STM... is for Save To Memory
you also have a POP... and a PUSH... microwords that are related to movem
(remember that movem was originaly provided to save and restore context (registers) to/from memory)
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M --> R
.W or .L
(An) ldmr1
(An)+ popm1
(d16,An) ldmd1
(d8,An,Xn) ldmx0
(xxx).W lmaw1
(xxx).L lmal1
R --> M
.W or .L
(An) stmr1
-(An) push1
(d16,An) stmd1
(d8,An,Xn) stmx1
(xxx).W smaw1
(xxx).L smal1Steven Seagal wrote:For MOVEM to Memory, does prefetch occur before writing to memory?
The answer to this one is in the Yacht Table I post two weeks ago !
Code: Select all
R --> M | |
.W | |
(An) | 8+4m(2/m) | np (nw)* np
-(An) | 8+4m(2/m) | np (nw)* np
(d16,An) | 12+4m(3/m) | np np (nw)* np
(d8,An,Xn) | 14+4m(3/m) | np n np (nw)* np
(xxx).W | 12+4m(3/m) | np np (nw)* np
(xxx).L | 16+4m(4/m) | np np np (nw)* np
.L | |
(An) | 8+8m(2/2m) | np (nW nw)* np
-(An) | 8+8m(2/2m) | np (nw nW)* np
(d16,An) | 12+8m(3/2m) | np np (nW nw)* np
(d8,An,Xn) | 14+8m(3/2m) | np n np (nW nw)* np
(xxx).W | 12+8m(3/2m) | np np (nW nw)* np
(xxx).L | 16+8m(4/2m) | np np np (nW nw)* npThe first batch of prefetches is from the <EA> evaluation the last prefetch is from the instruction execution.
Steven Seagal wrote:Are there microcodes for exceptions? What would be the name for 'bus error'?
As said in the answer of your first question :
BSERx is for address and bus errors exceptions
TRAPx is for trap exception but also for privilege violation exception and illegal instruction exception. It's the main routine used by all the other exceptions
and you also have :
RSTPx for reset exception
TRACx for trace exception
ITLXx for interrupt exception
TRPVx for trapv exception
CHK exception and divide by zero exception starts with the micro/nanowords dedicated to the instruction (CHK, DIVU or DIVS) and branch to TRAPx nanowords
Steven Seagal wrote:When the CPU needs the value in IRC, it may in fact read an intermediary register instead? (like 'dbin')
dbin is not a register but the data bus input buffer.
All the registers (external and intrnal) can, more or less (problems occur when needing to write a 32bit value in a 16bit register), be directly reached, read, written by the CPU.
aob (address bus output buffer), dob (data bus output buffer) and dbin (data bus input buffer) are used when we need to read/write to a specific address in memory (by the way : "input" and "output" must be understood in the CPU point of view).
Steven Seagal wrote:And when the CPU takes that IRC value (takes no read cycles), it fetches at once to fill it again, so that our timings are right?
I'm not sure you read correctly. IRC is never read. In instruction execution, IRC could be set one or many times form values that are on the data bus (and that can be read and used in the instruction execution either). You'll find "edb-->irc" and "(ir)-->ird" but no "(irc)-->ir". This last action occurs between two instructions decoding/execution. When prefetching we just change the value of IRC to the value of next word in the instruction flow.
Steven Seagal wrote:(sorry for all the questions!
No harm, it's a very interesting subject and it makes me fix some errors here and there on docs that I want to share later.
Re: Program counter and exception
More infos about bus error exceptions (data and address) :
from M68000UM 6.3.9 Bus Error :
from M68000UM 6.3.10 Address Error :
from M68000UM Figure 5-25. Bus Error Timing Diagram :
The instruction execution is always stopped on bus S4 (5th bus state of the read/write cycle on the bus). It's true for bus error and for address error. So the two exceptions are raised at the same time in instruction execution, when needed.
Each bus state is equivalent to 1/2 clock cycle. A read or write cycle on the bus lasts 4 clock cycles <--> 8 bus state when no errors occurs.
In common case, a nanoword execution lasts 2 or 4 cycles. In some cases, a nanoword that don't mess with the bus (let's call it "nop nanoword") can last 2 cycles or can pair with another nop nanoword to last 2 cycles.
In common case, nanowords that read or write on the bus last 4 cycles. In some rare cases a read or a write on the bus can be splitted on two paired nanowords and the result last 4 cycles. In all cases, the bus access is always done after the first 2 clock cycles. So the 4 clock cycles of a read or write cycle always leads to "nr" or "nw" in therm of nanowords usage of the bus (n is for nop, r is for read, w id for write, prefetch is a read cycle like any other).
Bus S4 is corresponding to the beginning of execution of the last (commonly second) nanoword (the one that write or read on the bus). Looking into nanocode these nanowords always starts with nanoinstruction that place value on aob and get value from dbin or put value on dob (putting an address on address bus and getting data from data bus or putting data on data bus).
In conclusion, unlike what I first thought, You can make this final statement a rule :
from M68000UM 6.3.9 Bus Error :
A bus error exception occurs when the external logic requests that a bus error be
processed by an exception. The current bus cycle is aborted. The current processor
activity, whether instruction or exception processing, is terminated, and the processor
immediately begins exception processing.
from M68000UM 6.3.10 Address Error :
An address error exception occurs when the processor attempts to access a word or longword
operand or an instruction at an odd address. An address error is similar to an
internally generated bus error. The bus cycle is aborted, and the processor ceases current
processing and begins exception processing.
from M68000UM Figure 5-25. Bus Error Timing Diagram :
The instruction execution is always stopped on bus S4 (5th bus state of the read/write cycle on the bus). It's true for bus error and for address error. So the two exceptions are raised at the same time in instruction execution, when needed.
Each bus state is equivalent to 1/2 clock cycle. A read or write cycle on the bus lasts 4 clock cycles <--> 8 bus state when no errors occurs.
In common case, a nanoword execution lasts 2 or 4 cycles. In some cases, a nanoword that don't mess with the bus (let's call it "nop nanoword") can last 2 cycles or can pair with another nop nanoword to last 2 cycles.
In common case, nanowords that read or write on the bus last 4 cycles. In some rare cases a read or a write on the bus can be splitted on two paired nanowords and the result last 4 cycles. In all cases, the bus access is always done after the first 2 clock cycles. So the 4 clock cycles of a read or write cycle always leads to "nr" or "nw" in therm of nanowords usage of the bus (n is for nop, r is for read, w id for write, prefetch is a read cycle like any other).
Bus S4 is corresponding to the beginning of execution of the last (commonly second) nanoword (the one that write or read on the bus). Looking into nanocode these nanowords always starts with nanoinstruction that place value on aob and get value from dbin or put value on dob (putting an address on address bus and getting data from data bus or putting data on data bus).
In conclusion, unlike what I first thought, You can make this final statement a rule :
When a bus error or an address error occurs, it always occurs on the beginning of the execution of the nanoword that read or write on the data bus (S4 bus state).
Every registers value modifications that have been done before this point (in previous nanowords execution) must be considered as done and effective.
Every registers value modifications that should be done after this point (in the current nanoword and the following ones if any) must be considered as not done and non effective.
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