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ppera wrote:As I see, GLUE chip by address decoding has relative big delay times, I assume in range about 30-50 nS.
Any info about it ? Can someone measure it with logic analyzer ? For instance delay between /AS and some ROM line activating when addressing ROM ?
P.S. STE has less delays by addr. decoding.
ppera wrote:Smartheads: why spamming this thread what is obviously above your knowledge and imagination ?
The reason why some need to know it: when designing some peripheral, for instance for cartridge port, GLUE delay time is important - in case of slower devices we can fast run out from some 250nS, what CPU has to fetch datas on bus.
Maybe some moderator action considering repeated rat bites ?
Rat boy wrote:Yet another pointless personal attack at myself by the same person...they're adding up. Well done.
CopperCAT wrote:You might want to ask someone who's involved with an atari fpga implementation, like Wolfgang of experiment-s or the guy from fpga-arcade. They have already RTL descriptions of the GLU chip so they should know
ppera wrote:Too bad we don't have option to ignore some people here...
ppera wrote:I don't think that concrete chip delay times are so relevant by designing some FPGA clone. What they need is cycle-accurate implementation. With modern, fast components delay times usually aren't problem.
CopperCAT wrote:ppera wrote:I don't think that concrete chip delay times are so relevant by designing some FPGA clone. What they need is cycle-accurate implementation. With modern, fast components delay times usually aren't problem.
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