For that matter I found the article from Alien on Overscan technique ( that I published at http://www.atari-forum.com/viewtopic.php?p=76804#76804 quite interesting and with a lot of useful information.
on page 10 he is mentioning:
0 Byte line by switching to 60Hz at position 14 (detection of the beginning of a line at 50Hz). This method is not recommended, because it doesn't work once out of every twenty times the ST is powered on. This happens when the timing of the GLUE and the MMU are offset in such a manner that the 68000 cannot access the bus on the precise cycle required to change the frequency. Recall that it is the MMU that decides which of every four cycles will be allocated to the 68000, and that at on power on circuits can receive parasitic noise on the clock signal that could potentially cause this offset.
and on page 14:
This actually occurs rarely (one time out of 20), depending on power up conditions causing the GLUE, MMU and SHIFTER to be slightly out of synch.
Therefore it seems that the "wakeup mode" as described in this document is more undeterministic/random (as confirmed by Paulo) than as described by Ijor to be related to temperature (when warm always the same wakeup mode). Note that the two are not antagonistic the temperature must definitively have some effect on a borderline behavior.
Unfortunately my STF does not have this randomness at wakeup. Otherwise I could have done some experiments (I have all the equipment to "freeze and/or to heat" the MMU and GLUE) ...
Actually to better understand what is happening I was wandering if anybody had analyzed the different signals involved with a logic analyzer?
Knowing exactly the relationship between the different clocks and signals would be invaluable in understanding the problem.
I have also updated the diagram that I have published at the beginning of this thread. It now shows the chain that generates the clocks (32Mhz input + 16MHz output of the shifter, 16MHz input + 8/4MHz output of the MMU, and 8MHz input + 2MHz/500KHz output of the Glue) as well as a more detailed presentation of the data/address busses (shows how the data busses are separated and latched/tri-stated under the control of the MMU). I have also shown the fact that the GLUE/MMU are connected to the DTACK signal and this is probably the signal used by the MMU to sometimes delay the 68000 (usually by by two cycles).
Therefore can someone provide detailed timing information for the different signals involved?
With the arrival of several USB Logic Analyzers the price has dropped and may be ....