Understanding the Union Demo's Opening of left and right borders

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Re: Understanding the Union Demo's Opening of left and right borders

Postby alien » Thu Dec 19, 2019 2:34 pm

TomH wrote:The quoted statement makes no qualitative claim about Ijor’s English at all, and indeed there are no grounds on which to do so. I can’t fault it, and haven’t. This is my first comment on it at all.


I'm glad that was a misunderstanding.

TomH wrote:“The table below lists the times at which certain tests are applied. If a test is passed, the consequence or consequences will apply at a time shortly afterwards. They will not necessarily occur simultaneously”.


That's clear. Thank you.
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Re: Understanding the Union Demo's Opening of left and right borders

Postby TomH » Thu Dec 19, 2019 3:09 pm

alien wrote:That's clear. Thank you.


Yeah, I mean it's not yet ideal, but it's a lot better than my extemporaneous version. I'm going to keep working on the wiki article too, e.g. it'd be nice to have the potential horizontal line lengths right up with the state machines, rather than on the far side of discussion of the vertical state machine and the Shifter, which will require some light rewriting for context.

Please don't hesitate to edit any language on the wiki.

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Re: Understanding the Union Demo's Opening of left and right borders

Postby ijor » Mon Jan 06, 2020 8:26 pm

TomH wrote:
alien wrote:The table shows at which cycle the GLUE tests the current frequency to decide if it will change the SYNC, BLANK & DE signals. The signals will actually change a little later, not necessarily synchronously.


Added many hours before you posted:

“The table below lists the times at which certain tests are applied. If a test is passed, the consequence or consequences will apply at a time shortly afterwards. They will not necessarily occur simultaneously”.


It is not an analog delay, which is what it is implied by "time shortly afterwards" or a "little later", or at the very least what might be interpreted. There is a synchronous delay between SYNC and DE. That's why I am using the term "cycle" all the time. HSYNC and DE don't change at the same cycle.

And again, no, I won't edit the wiki.
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Re: Understanding the Union Demo's Opening of left and right borders

Postby TomH » Wed Jan 08, 2020 6:30 pm

ijor wrote:
TomH wrote: “The table below lists the times at which certain tests are applied. If a test is passed, the consequence or consequences will apply at a time shortly afterwards. They will not necessarily occur simultaneously”.


It is not an analog delay, which is what it is implied by "time shortly afterwards" or a "little later", or at the very least what might be interpreted. There is a synchronous delay between SYNC and DE. That's why I am using the term "cycle" all the time. HSYNC and DE don't change at the same cycle.


I disagree on implication but agree on potential interpretation. It was meant to communicate only: there'll be delays, but I'm not going to tell you what they are, or even whether they're the same for every row.

I will seek a better phrasing.

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Re: Understanding the Union Demo's Opening of left and right borders

Postby ijor » Thu Jan 09, 2020 4:36 am

TomH wrote:It was meant to communicate only: there'll be delays, but I'm not going to tell you what they are, or even whether they're the same for every row.


I'm not sure there is any need to be that vague, at least regarding the simultaneity of multiple signals affected on the same row. Considering there is only one such case (LINE-50), it might be better to elaborate and be a bit more precise.
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Re: Understanding the Union Demo's Opening of left and right borders

Postby TomH » Thu Jan 09, 2020 3:05 pm

ijor wrote:
TomH wrote:It was meant to communicate only: there'll be delays, but I'm not going to tell you what they are, or even whether they're the same for every row.


I'm not sure there is any need to be that vague, at least regarding the simultaneity of multiple signals affected on the same row. Considering there is only one such case (LINE-50), it might be better to elaborate and be a bit more precise.


I'm not against being precise, I just don't know what the actual numbers are, so I was seeking only to clarify what information is in the article and what information shouldn't be taken as implied — you'll recall that a lot of my misunderstanding from earlier was falsely believing that if a test is at cycle n indicates that a signal should become active then the signal will become active at cycle n. So I primarily wanted to help future readers avoid that mistake (though, accepted, a better phrasing is necessary).

Especially as I think you've already been extremely helpful, and evidently I haven't been the best at asking questions, I'm hoping that a more thorough search of this forum's archives is going to throw some light on things.

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Re: Understanding the Union Demo's Opening of left and right borders

Postby ijor » Fri Jan 10, 2020 1:29 am

TomH wrote:Especially as I think you've already been extremely helpful, and evidently I haven't been the best at asking questions, I'm hoping that a more thorough search of this forum's archives is going to throw some light on things.


I think I understand your questions, and I think I answered them already. But here I'll try to elaborate again ...

What is the delay, and how many cycles take from the test to the actual signal's edge?

As I said, there is no strict answer, and, from a software point of view, you probably don't really care. There is no strict precise cycle that can be defined as when the test and the comparison is performed. Hardware doesn't work like that, it has pipeline and internal delays. Furthermore, when the CPU performs a write, a bus cycle takes four clock cycles. So which one of these four clocks is the cycle that the write is being performed?

What matters is the relation, the relative distance from one test/comparison to the other. This matter because this give you the line length. And the answer to this is obvious and trivial. E.g., for a normal 50Hz line that, according to the table, starts at cycle 56 and ends at cycle 376. The width of the DE pulse is simply, and obviously, 376 - 56 = 320 cycles. This is valid for all cases, except, for our LINE-50 entry which is a very special case ...

Are the H and DE signal activated simultaneously at LINE-50?

Once again, this is a very special case because here DE is affected only indirectly. There is no test at this point to change the DE state at all. The only test at this point is for asserting HSYNC. What happens is that whenever HSYNC is asserted, DE is deasserted after a synchronous delay. This happens no matter the resolution or the previous value of the horizontal counter.

For the purpose of computing the line length, the DE timing here is as if there was an extra delay of two cycles. You consider then DE to be disabled at LINE-48. This gives you the full screen line length = LINE-48-4 = 512-52 = 460 cycles.

And once again, the absolute cycle numbers on the table are just a convention. They don't have any real meaning and I honestly don't even know their origin. But I trust Troed that this was the convention used by most programmers.
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Re: Understanding the Union Demo's Opening of left and right borders

Postby TomH » Fri Jan 10, 2020 3:53 am

ijor wrote:
TomH wrote:Especially as I think you've already been extremely helpful, and evidently I haven't been the best at asking questions, I'm hoping that a more thorough search of this forum's archives is going to throw some light on things.


I think I understand your questions, and I think I answered them already. But here I'll try to elaborate again ...


Sorry, yes, I understood those answers already — you were very clear and informative. I think you're right that if the issue is raised at all then it should be dealt with as correctly as possible, and my instinct here has been incorrect.

Not that it matters, or in any way affects the point you've made, but my instinct was that there are plenty of what-happens-next questions left dangling* and that I didn't want to get further into it when I don't know the answers. This, of course, is the wrong thing to think because what I've already written could easily be more precise in the same amount of space. As we've agreed, it's a little prone to mislead as it currently is.

* mostly about when the relevant feedback from each event will affect the software side of the world — interrupts, changes in the polled video address, etc. Much more than is currently in the wiki page, and please don't feel the need to pursue this stuff, as it's fairly digressive and starts to get somewhat remote from the point of the article.

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Re: Understanding the Union Demo's Opening of left and right borders

Postby ijor » Wed Jan 15, 2020 12:54 am

TomH wrote:Sorry, yes, I understood those answers already — you were very clear and informative.


So if you know the answers, then why you are that vague:

They will not necessarily occur simultaneously.


You know they are not simultaneous. Why using such phrasing that is not conclusive?

Sorry, but to be honest, I think it is more confusing now than it was before your corrections. I would remove completely the reference about the delay, it doesn't add anything, IMHO, quite the contrary. It is important to note the special case of the row LINE-50 one way or the other. Either mention that there is a delay and DE and HSYNC do not change in the same cycle, or elaborate more if you want.

From the wiki (bolding is mine):
The path from DE via Timer B to the 68000's interrupt input is subject to both a latency in reaching the MFP and in the MFP responding to the change in its input.


Where did you get that there is delay from GLUE to the MFP? Or do you mean something else?
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Re: Understanding the Union Demo's Opening of left and right borders

Postby TomH » Wed Jan 15, 2020 6:35 pm

ijor wrote:Sorry, but to be honest, I think it is more confusing now than it was before your corrections. I would remove completely the reference about the delay, it doesn't add anything, IMHO, quite the contrary.


I strongly disagree. Furthermore, it's a wiki so there's a full edit history so nothing has been lost. If someone else agrees with you and wants to do something about it then it's an easy fix. So — obiter — even if I did agree, it would be invalid to argue that any damage had been done.

Amongst the article's many deficiencies as previously written:
  • opening with authoriship and greetings;
  • making sudden digressions into the history of when information was acquired, prior to having presented the information;
  • alleging that "By following the logic described here it's possible to implement emulators and simulators that will be able to run existing Atari ST and STE programs that make use of "sync tricks" to create fullscreens and sync scrollers", presenting pseudocode like "IF(60) BLANK = FALSE" but apparently expecting a reader who is implementing an emulator or simulator to assume that means "IF (60) BLANK = FALSE ... at some point in the future, I'm not going to tell you when", and for that to be sufficient to "be able to run existing Atari ST and STE programs that make use of "sync tricks""; and
  • being formed as: ST horizontal state machine, detour into wakestates, back to horizontal state machines for the STE, onto the vertical state machine, back to horizontal discussion for the shifter state machine, then back to the GLUE state machine again to discuss potential sync line lengths.

So — quite apart from the many extraneous digressions — it fundamentally didn't achieve its stated aim. Following the logic therein is in fact hugely insufficient for implementing emulators and simulators that are able to run existing ST and STE programs that make use of "sync tricks".

The fact that you want the word 'necessarily' removed from the sentence "They will not necessarily occur simultaneously" is a somewhat negligible complaint in comparison. It doesn't support the conclusion. (EDIT: word removed though; no disagreement that it adds nothing; disagreement here is on the overreach of "quite the contrary")

I don't intend to address your other issues as I don't want to drag other authors into it. Suffice to say, if you search the forum for references to 28 cycles as a rule of thumb on Timer B interrupts, you'll find the source pretty easily.

EDIT: noted for fairness, I am continuing to respond to criticism by editing the article. I have just made edits in response to the post above. If you're an independent reader, don't judge Ijor's comments by the current version, or my responses above. He was most recently writing about this version versus this one. Neither is now current. Such is wiki life.

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Re: Understanding the Union Demo's Opening of left and right borders

Postby ijor » Wed Jan 15, 2020 7:51 pm

TomH wrote:I strongly disagree. Furthermore, it's a wiki so there's a full edit history so nothing has been lost. If someone else agrees with you and wants to do something about it then it's an easy fix. So — obiter — even if I did agree, it would be invalid to argue that any damage had been done.

Amongst the article's many deficiencies as previously written:
...
The fact that you want the word 'necessarily' removed from the sentence "They will not necessarily occur simultaneously" is a somewhat negligible complaint in comparison. It doesn't support the conclusion. (EDIT: word removed though; no disagreement that it adds nothing; disagreement here is on the overreach of "quite the contrary")


I wasn't talking about all the editions you made to the wiki page. I didn't even check thoroughly all your changes. I was all the time talking about the issue we were discussing in this thread, the horizontal state machine table and the issue of the delay and simultaneity.

After your current edition it's better, IMHO. So no need to argue if we agree, or it seem so at least. I would elaborate a little more about the LINE-50 entry specifically. But this is not your fault and I cannot complain about that.

I don't intend to address your other issues as I don't want to drag other authors into it. Suffice to say, if you search the forum for references to 28 cycles as a rule of thumb on Timer B interrupts, you'll find the source pretty easily.


I searched and I couldn't find the source you are talking about. Never mind that and once again. If you meant that the DE signal has a delay from GLUE to the MFP, then there is nothing significant. I never said that the rule of thumb is wrong, I didn't even quote that sentece.
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Re: Understanding the Union Demo's Opening of left and right borders

Postby TomH » Wed Jan 15, 2020 8:02 pm

ijor wrote:I wasn't talking about all the editions you made to the wiki page.

Okay, then it's pretty clear: I'm way off the mark here in my tone and manner of response. That's my fault, and something I need to work on.

ijor wrote:I searched and I couldn't find the source you are talking about. Never mind that and once again. If you meant that the DE signal has a delay from GLUE to the MFP, then there is nothing significant. I never said that the rule of thumb is wrong, I didn't even quote that sentece.

I've adjusted it to "a latency in being signalled to the MFP and in the MFP responding to the change in its input" to clarify that I don't think electrons are somehow having a bit of a nap halfway along a trace or anything like that.

I intend this to be consistent with your comment elsewhere, a long time ago:
ijor wrote:Timer B interrupt lattency is related to GLUE, MFP and CPU delays.


I've phrased the article in terms of delay in signalling the interrupt to the CPU since when the 68000 samples the interrupt input respective to current instructions is obviously a huge topic on its own and, I think, not best covered on that page.

Otherwise I think it's now in-line with that sentence I dredged up from forever ago, which I've selected here not because it's by you but because it's genuine the most in-depth explanation I've found in searching. There's that bit in the MFP datasheet about the change in input needing to be stable for four [MFP] cycles before it'll be recognised, which puts a floor on the MFP's side of the equation but doesn't fully specify it: recognising that the input has changed is one thing, decrementing Timer B and checking whether an interrupt request should ensue is something else for which no timing is given. If you add that to the usual question mark over anything written in a datasheet and not confirmed empirically, I'm not sure there's enough concrete information there to draw much from.

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Re: Understanding the Union Demo's Opening of left and right borders

Postby ijor » Thu Jan 16, 2020 3:51 am

TomH wrote:I've adjusted it to "a latency in being signalled to the MFP and in the MFP responding to the change in its input" to clarify that I don't think electrons are somehow having a bit of a nap halfway along a trace or anything like that.

I intend this to be consistent with your comment elsewhere, a long time ago:
ijor wrote:Timer B interrupt lattency is related to GLUE, MFP and CPU delays.



I never meant that GLUE contributes to the interrupt latency at the DE path. I meant about the delay when processing the INTR signal from the MFP into the IPLx signals to the CPU. However I corrected myself later, IIRC in the very same thread. That GLUE delay is present, of course, GLUE needs some time to process INTR. But it's a very small combinatorial delay that is not very significant.

Aside from the CPU latency itself, almost the whole latency is inside the MFP.
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