68000 weird out of order reads?

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Zakaleth
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68000 weird out of order reads?

Postby Zakaleth » Tue Dec 12, 2017 8:02 pm

Hi all, I recently hooked up my ST to my logic analyser. I sampled the Address, clock, reset and AS lines of the 68000 at 100MHz

Immediately, I see what I consider odd behaviour. Here's the first few bytes of TOS disassembled.

Code: Select all

fc0036:   0cb9 fa52 235f  cmpil #$fa52235f,0xfa0000
fc003c:   00fa 0000
fc0040:   660a            bnes 0xfc004c


Here's the Address bus traffic I see:

Code: Select all

1  FC0036
2  FC0038
3  FC003A
4  FC003C
5  FC003E
6  FC0040
7  FA0000
8  FA0002


Lets look at that in the context of the disassemly:

Code: Select all

Lines 1 to 5 are the cmpi.l instruction fetch
1  FC0036 0cb9
2  FC0038 fa52
3  FC003A 235f
4  FC003C 00fa
5  FC003E 0000

Now here's where it gets strange. This is a fetch of the bnes
6  FC0040

Then we see the bus access from the cmp instruction to read the long at fa0000
7  FA0000
8  FA0002


What's going on here!? Why is there a fetch of the instruction at FC0040 (BNES) before the fetches for the CMP instruction? Why is this completely out of order?
I would expect to see the following:

Code: Select all

1  FC0036 cmpi.l
2  FC0038
3  FC003A
4  FC003C
5  FC003E

6  FA0000 cmp.i read of address fa0000
7  FA0002

8  FC0040 fetch of bnes instruction




Could someone please enlighten me here as to what may be happening?

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Re: 68000 weird out of order reads?

Postby ijor » Wed Dec 13, 2017 4:08 am

It has to do with how the microcode works. There are many cases like this.

I would need to double check it to be sure. But IIRC, in this case the (apparent) reason is that the CPU needs an extra cycle to process the operand address before actually reading. This again has to do with how the microcode works. And if it can't read the operand immediately, then it is more efficient to use the bus for the next instruction prefetch than keeping the bus idle.

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Re: 68000 weird out of order reads?

Postby AtariZoll » Wed Dec 13, 2017 4:49 am

Isn't this case what we call 'prefetch' ? I see Steven Seagal coming here soon :-)
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Re: 68000 weird out of order reads?

Postby Zakaleth » Wed Dec 13, 2017 12:38 pm

Thanks for the replies guys. Does anyone know of any documentation regarding this? A doc showing how the 68000 instructions are broken down into microcode would be awesome too.

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Re: 68000 weird out of order reads?

Postby ijor » Wed Dec 13, 2017 1:20 pm

Zakaleth wrote:Thanks for the replies guys. Does anyone know of any documentation regarding this? A doc showing how the 68000 instructions are broken down into microcode would be awesome too.


The closer to an official documentation is US patent: 4,325,121

Be warned that the scans are barely readable, it has some errors, and it covers a preliminary (probably unreleased) version of the CPU with some slight differences with the product as we know it. Having said that, it is an invaluable resource and an awesome read.

AtariZoll wrote:Isn't this case what we call 'prefetch' ?


Not really. Prefetch just means that instruction fetching is performed before the instruction starts executing. It doesn't necessarily means that it has to be performed before accessing the operand of the previous instruction, as it happens in this case. And as a matter of fact in many cases the prefetch is performed after accessing the operand, not before like in this case.

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Re: 68000 weird out of order reads?

Postby czietz » Wed Dec 13, 2017 1:23 pm

How the 68000 does its prefetch is explained in this detailed article by ijor: http://pasti.fxatari.com/68kdocs/68kPrefetch.html
Probably the most comprehensive guide about the bus cycles done by each instruction is Yacht.txt: https://github.com/larsbrinkhoff/m68k-m ... /Yacht.txt
As for the actual microcode: much of it is documented in the Motorola patents (USP4325121 etc.); however this is definitively not light reading.

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Re: 68000 weird out of order reads?

Postby Zakaleth » Wed Dec 13, 2017 1:43 pm

Beautiful! Thanks so much guys. I wasn't aware that the 68000 had any sort of prefetch or used microcoded instructions. I've got a lot of interesting reading ahead of me :)

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Re: 68000 weird out of order reads?

Postby Steven Seagal » Wed Dec 13, 2017 8:31 pm

Here's the YACHT table for CMPI:

Code: Select all

-------------------------------------------------------------------------------
                  |    Exec Time    |               Data Bus Usage
       CMPI       |  INSTR     EA   | 1st Operand |  2nd OP (ea)  |   INSTR
------------------+-----------------+-------------+-------------+--------------
#<data>,<ea> :    |                 |             |               |
  .B or .W :      |                 |             |               |
    Dn            |  8(2/0)  0(0/0) |          np |               | np         
    (An)          |  8(2/0)  4(1/0) |          np |            nr | np         
    (An)+         |  8(2/0)  4(1/0) |          np |            nr | np         
    -(An)         |  8(2/0)  6(1/0) |          np | n          nr | np         
    (d16,An)      |  8(2/0)  8(2/0) |          np |      np    nr | np         
    (d8,An,Xn)    |  8(2/0) 10(2/0) |          np | n    np    nr | np         
    (xxx).W       |  8(2/0)  8(2/0) |          np |      np    nr | np         
    (xxx).L       |  8(2/0) 12(3/0) |          np |   np np    nr | np         
  .L :            |                 |             |               |
    Dn            | 14(3/0)  0(0/0) |       np np |               | np       n 
    (An)          | 12(3/0)  8(2/0) |       np np |         nR nr | np         
    (An)+         | 12(3/0)  8(2/0) |       np np |         nR nr | np         
    -(An)         | 12(3/0) 10(2/0) |       np np | n       nR nr | np         
    (d16,An)      | 12(3/0) 12(3/0) |       np np |      np nR nr | np         
    (d8,An,Xn)    | 12(3/0) 14(3/0) |       np np | n    np nR nr | np         
    (xxx).W       | 12(3/0) 12(3/0) |       np np |      np nR nr | np         
    (xxx).L       | 12(3/0) 16(4/0) |       np np |   np np nR nr | np         


According to it, the operand is read before prefetch.
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Re: 68000 weird out of order reads?

Postby ijor » Thu Dec 14, 2017 2:18 am

Steven Seagal wrote:Here's the YACHT table for CMPI:
...
According to it, the operand is read before prefetch.


The operand is read before prefetching the second word of the next instruction, but after the first word with the actual opcode (remember each instruction starts with two words on the prefetch queue). That was what the OP was seeing and asking the reason.

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Re: 68000 weird out of order reads?

Postby Steven Seagal » Thu Dec 14, 2017 7:57 am

But then it's just normal prefetch at work? I was thinking maybe it was a special case revealed by microcodes (and beginning to panic :) ).

Maybe the last prefetch is missing in OP:

Code: Select all

1  FC0036
2  FC0038
3  FC003A
4  FC003C
5  FC003E
6  FC0040
7  FA0000
8  FA0002
9  FC0042
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