SHIFTER reimplementation on FPGA

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ijor
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Re: SHIFTER reimplementation on FPGA

Postby ijor » Tue Aug 14, 2018 7:34 pm

Smonson wrote:So to make a stand-alone shifter with the Altera parts I can access in this old version of Quartus, I guess it would basically need all the same hardware as the HDMI board: 16 pins of bidirectional level shifters, 9 pins of downward level shifters and 10 upward level shifter for the clock and RGB (as well as the 32MHz oscillator).


Btw, out of curiosity, what are you using for the bidirectional level shifters? Digital transparent switches or buffered transceivers?

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Re: SHIFTER reimplementation on FPGA

Postby Smonson » Tue Aug 14, 2018 10:30 pm

I'm using a transceiver (74ALVC164245) for the data bus. The 5-to-3.3 shifters are 74LVC245s and the 16MHz clock is buffered at the socket with an MC74VHC1GT125.

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Re: SHIFTER reimplementation on FPGA

Postby ijor » Wed Aug 15, 2018 1:26 am

Smonson wrote: ... the 16MHz clock is buffered at the socket with an MC74VHC1GT125.


I wonder if this is really needed. Did you happen to test without it? I'm not suggesting to not use a level shifter and it certainly improves the noise margin, but just curious because TTL compatible output levels probably work.

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Re: SHIFTER reimplementation on FPGA

Postby Smonson » Wed Aug 15, 2018 2:47 am

I didn't test without it, but I had a huge amount of noise on my original prototype (that used stripboard) to the point where it rarely functioned. With the 3.3v clock passing through an unshielded ribbon cable, it seems worth having it. It's only a 40c part, and it's tiny (3x2.5mm), so not too many downsides. For something as important as the primary clock, especially.


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