HBS240/640 L1 design

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Arne
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HBS240/640 L1 design

Postby Arne » Tue Aug 20, 2019 6:03 am

Hi,
lately I have been wondering about the cache design of the HBS20/640 68k speeders.
And two things puzzle me:
  1. both do have a jumper to (de-)activate the cache. So it can be enabled while booting. Now how does this work when TOS is doing its memory test? It would write a bit pattern at address xy and the pattern would be written to main-memory and the L1. But when reading the pattern back for comparison the L1 would deliver the data, hence TOS would always assume a 4MB ST.
  2. the HBS640 manual claims that it is using 64KB cache for data and instructions. And indeed two KM682578 32K x8 SRAMS are populated on the PCB. But still they use 8K x8 71B74 tag RAMs. I checked the KM682578 A14 line and it is indeed connected to CPU's A15 - which is what I would expect. So it's probably not "fake news" i.e. populating 64KB and just using 16KB for marketing reasons.

thanks, Arne

Edit: regarding 2. : https://en.wikipedia.org/wiki/Amstrad_CPC#CPC472 :lol:
Last edited by Arne on Tue Aug 20, 2019 6:59 am, edited 1 time in total.
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czietz
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Re: HBS240/640 L1 design

Postby czietz » Tue Aug 20, 2019 6:41 am

Arne wrote:both do have a jumper to (de-)activate the cache. So it can be enabled while booting. Now how does this work when TOS is doing its memory test? It would write a bit pattern at address xy and the pattern would be written to main-memory and the L1. But when reading the pattern back for comparison the L1 would deliver the data, hence TOS would always assume a 4MB ST.


Would it? Essentially, TOS writes a test pattern to address X and tries to read it back from a different address Y. As long as Y is always a cache miss, data comes from memory and the RAM sizing works as usual.

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Arne
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Re: HBS240/640 L1 design

Postby Arne » Tue Aug 20, 2019 6:52 am

Good point!
To be more precise: I was referring to a statement in the Mach16 DIY article:
Damit die Daten im Cache-Speicher immer denen im Hauptspeicher entsprechen, muß man sie natürlich auch bei Schreibzugriffen aktualisieren. Dabei werden gleichzeitig der Cache- und der Hauptspeicher mit eimem acht Takte dauerndem Buszyklus beschrieben (Write Through Cache). Bei dieser Realisierung erfolgt allerdings nur die Auffrischung der schon im Cache vorhandene Daten. Das hat den Vorteil, daß das Cache auch schon beim Speichertest während des Kaltstarts des ST aktiv sein kann. Zur Erklärung: Die Speichertestroutine bestimmt die Speicherbelegung durch Beschreiben und anschließendes Probelesen von einzelnen Adressen. Würde nun durch jeden Schreibzugriff direkt das Cache aktualisiert, erhielte man immer das Ergebnis, daß der ST mit vier MByte bestückt sei.

But I wouldn't be surprised if parts of the article actually aren't true. Just mentioning it as it claims to boot with activated L1 (as HBS, too).
But what about the TOS 2.06 memory test (the '-' bar)?
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czietz
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Re: HBS240/640 L1 design

Postby czietz » Tue Aug 20, 2019 7:34 am

Arne wrote:But what about the TOS 2.06 memory test (the '-' bar)?


I suppose that would in fact only test the cache, if enabled. However imho that's more of an optical gimmick, anyway.

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Re: HBS240/640 L1 design

Postby SteveBagley » Wed Aug 21, 2019 12:44 pm

Arne wrote:
  1. the HBS640 manual claims that it is using 64KB cache for data and instructions. And indeed two KM682578 32K x8 SRAMS are populated on the PCB. But still they use 8K x8 71B74 tag RAMs. I checked the KM682578 A14 line and it is indeed connected to CPU's A15 - which is what I would expect. So it's probably not "fake news" i.e. populating 64KB and just using 16KB for marketing reasons.


It'd make sense if there were four TAG RAM chips, since the cache tag would be 8-bits wide (A23-A16), and so the four 8K TAG chips could be arranged to form 32K to store the TAG (with the SRAM arranged as 32Kx16 to store the cache line…

With just 16K of TAG RAM, I wonder if they are treating it as 16Kx32-bit wide cache with a 32-bit cache line, but I think the logic for building that (given the ST's 16bit data bus) would be nightmare-ish -- you'd need to do two reads from ST RAM for every cache miss.

This is assuming its a direct-mapped cache, of course.

Steve


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