lately I have been wondering about the cache design of the HBS20/640 68k speeders.
And two things puzzle me:
- both do have a jumper to (de-)activate the cache. So it can be enabled while booting. Now how does this work when TOS is doing its memory test? It would write a bit pattern at address xy and the pattern would be written to main-memory and the L1. But when reading the pattern back for comparison the L1 would deliver the data, hence TOS would always assume a 4MB ST.
- the HBS640 manual claims that it is using 64KB cache for data and instructions. And indeed two KM682578 32K x8 SRAMS are populated on the PCB. But still they use 8K x8 71B74 tag RAMs. I checked the KM682578 A14 line and it is indeed connected to CPU's A15 - which is what I would expect. So it's probably not "fake news" i.e. populating 64KB and just using 16KB for marketing reasons.
Edit: regarding 2. : https://en.wikipedia.org/wiki/Amstrad_CPC#CPC472