slingshot wrote:I don't see a flip-flop in LT2, just that one latch.
The whole LT2 cell works like a flip-flop. Or you mean that there is no flip-flop INSIDE
LT2? If so, Agree. What I meant by the extra flip flop is the one after the counter that pipelines the LOAD control signal.
And I see it's a bit different between 4081.pdf and 4081org.pdf, the former is simpler.
Seem different standard cell technology. In one case the flops require both the inverted and the non inverted clock, in the other they don't. I don't remember for sure why one has the "ORG" prefix. Christian?
We don't know for sure exactly which version, if at all, is the one on that is actually on the silicon. And there are multiple chip releases as well.
The extra flip-flop at the horizontal counter at the end of the chain ensures that the load will happen after the overflow state (e.g. there will be 127, 0, load value, ... states in the counter, not just 127, load value, ...).
But you don't need that strictly, not as long as load is synchronous. You could overflow on 127 and avoid that extra flip flop. Just compensate with an extra cycle on the reload values. This is exactly what ST GLUE does (see below). OTOH, if load is asynchronous, the extra flip flop must be present or you will get a combinational loop.
For me, it seems load of LT2 is just selecting the latch input between L and DC with L.
Not exactly. Yes, of course that at the end L selects between DC and DL. But because the way it is implemented, DL input is not fully synchronous.
When C is high (positive phase of the clock) and L is asserted as well, the following happens inside LT2 (sory for being too lazy to perform a simulation):
Bottom mux outputs DL.
Top mux outputs the output of the bottom mux (DL).
Then the D input of the latch will be NOT DL.
And because the latch is low active, latching would be enabled and the XQ output will be DL.
So the final Q output of the LT2 cell is DL. The DL input propagates to the output asynchronously, on the same cycle. This is contrary to the DC input that is fully synchronous.
This is ST GLUE logic (extracted from my code, developed from decap analysis):
Code: Select all
logic [6:0] hsLoad;
unique case( freq)
2'b00: hsLoad = 7'h01; // 60 Hz 508 cycles
2'b01: hsLoad = 7'h00; // 50 Hz 512 cycles
2'b11: hsLoad = 7'h48; // 70 Hz 224 cyles
reg [6:0] hsCntr;
wire hsReload = (& hsCntr);
always @( posedge clk2) begin
if( hsReload) hsCntr <= hsLoad;
else hsCntr <= hsCntr + 1'b1;