slingshot wrote:Anyone knows the exact number of wait states the GLUE applies for _writes_?
Probably just for the record, it is not GLUE, it is MMU
. I assume your question is related to the MiST core, so you probably don't care too much if it is GLUE or MMU.
Wait states for write and read RAM cycles are identical.
I know, the write data is latched ASAP (when exactly? At the first write cycle, when ASn and RWn goes low, or in the second, where UDSn and/or LDSn, too?), then when DTACKn is issued?
So if I divide the full memory cycle (CPU + Shifter) to 4 8 MHz CPU cycles, I'd like to fill this table:
RAM access is interleaved between CPU and Video cycles. Or more precisely, between cycles internals to the SHIFTER-RAM bus, and external cycles. Internal cycles are not only video load cycles but also ram refresh and, for the STe, sound DMA. External cycles, besides CPU, are DMA and Blitter cycles.
The exact phasing of this interleave is not so simple and can't easily be described in words. There are buffers and latches between the CPU and RAM. A waveform is needed if you really need to see the whole details. But again, for the MiST core you probably don't care. What you need to know is the following:
MMU assigns specific slots for each 4 8MHz cycles. A CPU cycle must start at the specific slot that it was assigned. Otherwise MMU inserts wait states forcing the CPU bus cycle to align to the slot. So, if you start counting 8MHz cycles from power up, CPU cycles must start at any cycle that is an exact multiple of 4, otherwise wait states would be inserted. The number of wait states would be one, two, or three cycles such as to force the ram access to start in the next 4 cycles boundary.
Read and write cycles are identical regarding the alignment and number of wait states.