Dead MegaST

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Arne
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Dead MegaST

Postby Arne » Wed Jan 30, 2019 4:24 pm

Hi Folks,

I got this MST with strange behavior. It won't boot at all and cycles through the same "signal loop" i.e. every 8µs (= 64 CLK8) it shows the same picture on the scope:
Image

I checked other signals (with the pink colored probe) which are:
/DTACK = always 1
/HALT = always 1 (except whe Reset button is pushed)
/RESET = always 1 (except whe Reset button is pushed)
/UDS = /LDS = R/W = /AS (regarding level and timing)
A[1..23] = always 1

So it looks like the 68000 wants to write a 16bit word at $FFFFFE! Of course the missing /DTACK upsets Glue and it pulls /BERR low after 64 CLK8.

CPU, MFP, PSG and FDC got sockets at some time - there might be a problem here. But I cannot locate it.
I checked the signal lines from CPU -> Glue -> MFP by now. Looks fine.
Blitter is removed and both solder bridges are closed.
And yes: I cleaned the PLCC sockets and swapped ICs with working ones from a 1040

Any idea?
Image

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Re: Dead MegaST

Postby czietz » Wed Jan 30, 2019 5:45 pm

If you release the reset button, does this loop start immediately or does the CPU first do something else?

If RW wasn't low, I would say that you are seeing an Interrupt Acknowledge Cycle. That one can have A23...1 all high. What's the level of the FC2...0 outputs of the CPU? What's the level of the /IPL2...0 inputs?

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Arne
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Re: Dead MegaST

Postby Arne » Wed Jan 30, 2019 8:41 pm

Thanks for the suggestions. I moved the board to inspect the bottom side and since I pressed the PSG into its socket I cannot recreate the scenario again :-/
The system behaves now without any signal change on any signal at all, except /HALT and /RESET when pressing the Reset button.
/BERR is constantly high, so all other beforementioned signals.
According to your suggestions I checked FC and IPL. FC is 0b111 and IPL is 0b011. So there is a IRQ level 4 asserted.

Image
(In red are the levels of the GI signals)

/GI[2..1] are connected to Glue /IPL[2..1]. For some reason /GI2 is constantly low - even while resetting the machine.
The 74LS148 seems to work as it outputs an /IPL of 0b011.

MFP asserts IRQs of level 6 but which ASIC asserts IRQ level 4? Glue itself?
Image

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Re: Dead MegaST

Postby czietz » Wed Jan 30, 2019 8:52 pm

Arne wrote:MFP asserts IRQs of level 6 but which ASIC asserts IRQ level 4? Glue itself?


Yes, Glue does that. Since it also generates video timing, it knows when to assert the level 4 (=vsync) interrupt. However, after reset the CPU will discard anything but level 7 interrupts. Therefore, a level 4 interrupt will not be an issue.
Also, if you say that now not even /AS strobes anymore, I think that the CPU does not even start. Check the 8 MHz clock, the 5V power supply and ground connection directly at the CPU.

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Re: Dead MegaST

Postby Arne » Wed Jan 30, 2019 9:06 pm

CLK8 looks fine just doesn't reach 0V

Image

GND/Vcc on CPU is at 4.9V
Image

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Re: Dead MegaST

Postby Arne » Wed Jan 30, 2019 9:39 pm

Everytime I touch the board it's getting worse.
Now I don't have a CLK8 anymore - it's constantly high. CLK4 is constantly low. CLK16 into MMU OTOH is fine. I put the MMU into a 1040 and the system boots properly...
Image

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Re: Dead MegaST

Postby Greenious » Thu Jan 31, 2019 12:37 am

Did you get the MST in this condition?

Is TOS ok? configured correctly for 2-chip/6-chip TOS?

If clk16 is fine, I suspect you got a connection problem in the mmu socket, clean the connectors and gently bend out the pins in the socket and/or mmu. I use isopropanol.
Updated my guides as of june 28th, 2016. Check'em out and feedback!
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Re: Dead MegaST

Postby Arne » Fri Feb 01, 2019 9:53 am

Back in business - repaired the CLK8. It still won't go down to 0V. Lowest peak I see on the scope is around 600mV.
Usually clocks on the Ataris I saw so far undershoot GND by >1V. Will check it on a 1040 later.

I see the /HALT signal come and go. /RESET is high. When pushing the Reset button both go low as expected and rise as expected.
There is no constant delay between these /HALT glitches. They come and go.
I doubt it's the 7407 OCing both signals as they behave as expected (no glitches) when CPU is removed.

Image

In detail:

Image

And the logic analyser's output:

Image
(Bus1 and Bus3) are A[23..1] with an additional "virtual" A0 being low all the time. So the sampled address is $FFFFFE.

Any idea what may be responsible for the issue?
Image

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Re: Dead MegaST

Postby czietz » Fri Feb 01, 2019 5:14 pm

But wait: The moment /AS, /UDS and /LDS go low, the address is not $FFFFFE, anymore. It is $00something -- the zoom level does not allow to read the lower 16 bits. To me, this looks like normal start after RESET (if you ignore what the HALT line does before). The CPU tries to read from address 0. But then something fails.

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Re: Dead MegaST

Postby Arne » Fri Feb 01, 2019 6:37 pm

As I said the CLK8 generated by MMU didn't look like what I expected.
This is it:

Image

I had the feeling that I should rework the CLK8 so I put a 74F32 on top of the 74LS11 next to MMU and
wired it like this:
Image

R113 is the original 33R resistor next to MMU.

This gives me this:
Image

Blue showing the CLK8 after it has passed R113, yellow the CLK8 generated by MMU.
The new CLK8 looks worse than on the first picture but.... the testkit now outputs data
via RS232.
So I can just speculate that the /HALT "dancing" had something to do with CLK8.
Image

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Re: Dead MegaST

Postby Arne » Sun Feb 03, 2019 8:02 pm

So I am narrowing down the source of the CLK8 problem - at least I think so.
I have reworked the CLK8 generated by MMU so that I totally ignore its CLK8 and use CLK16
to feed at frequency divider (74F74) and use its output as the new CLK8.
Gives me a nice clock with 4V at its highest and only 200mV undershoot.

Image

As soon as the FDD powers up the CLK8 drops significantly and will not rise after FDD access!

Image

The screen turns black (HiRes) and HSYNC/VSYNC go to 5V constantly. Glue does no generate 500kHz and 2MHz clocks anymore.
Even a reset will not cure the problem. It needs a shutdown. I am using a PC AT PSU (230W) with 4.9V on the MegaST mainboard.

If I switch the WD/VLSI for an Ajax it becomes better:

Image

Nonetheless CLK8 drops again on FDD access:

Image

and then it goes into a reset loop back to the third picture.
Image

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Arne
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Re: Dead MegaST

Postby Arne » Sat Feb 16, 2019 8:43 am

So I got it running to some point.
With test-kit it performs:
R - RAM: OK
D - DMA: OK
T - Timing: OK
S - Serial: OK
M - MIDI: OK
F - Floppy: Quick Test: OK
F - Floppy: Extensive test: fail

Code: Select all

F6 Read compare error 0200 4200 Track 00          Sector 10
F6 Read compare error 0300 4300 Track 00          Sector 10
F6 Read compare error 0400 4400 Track 00          Sector 10
F6 Read compare error 0500 4500 Track 00          Sector 10
F6 Read compare error 0600 4600 Track 00          Sector 10
F6 Read compare error 0700 4700 Track 00          Sector 10
F6 Read compare error 0800 4800 Track 00          Sector 10
F6 Read compare error 0900 4900 Track 00          Sector 10
F6 Read compare error 0A00 4A00 Track 00          Sector 10
Reading    Side 0 Track 79         
F6 Read compare error 0200 4200 Track 79          Sector 10
F6 Read compare error 0300 4300 Track 79          Sector 10
F6 Read compare error 0400 4400 Track 79          Sector 10
F6 Read compare error 0500 4500 Track 79          Sector 10
F6 Read compare error 0600 4600 Track 79          Sector 10
F6 Read compare error 0700 4700 Track 79          Sector 10
F6 Read compare error 0800 4800 Track 79          Sector 10
F6 Read compare error 0900 4900 Track 79          Sector 10
F6 Read compare error 0A00 4A00 Track 79          Sector 10
Reading    Side 0 Track 46         
F6 Read compare error 0200 4200 Track 46          Sector 10
F6 Read compare error 0300 4300 Track 46          Sector 10
F6 Read compare error 0400 4400 Track 46          Sector 10
F6 Read compare error 0500 4500 Track 46          Sector 10
F6 Read compare error 0600 4600 Track 46          Sector 10
F6 Read compare error 0700 4700 Track 46          Sector 10
F6 Read compare error 0800 4800 Track 46          Sector 10
F6 Read compare error 0900 4900 Track 46          Sector 10
F6 Read compare error 0A00 4A00 Track 46          Sector 10
(...)

... and so on on the other tracks aswell.
I checked the PCB wiring between DMA <-> FDC/PSG <-> Shugart bus. It's fine as far as I can tell.
So according to the error log bit 14 is always stuck to 1. But as the data stream between FDC and
Shugart bus is serialied I have no clue why it's always bit 14.
I exchanged for known working parts:
CPU, Chipset, MFP, PSG, FDD, Disk, Shugart cable.
With test kit disabled it shows a white screen (SM124) and resets after about 4-5 sec.

Any useful hints?

Edit:
With the help of an LA I have been able to track down the resets.

Image
Forget about the /ROM2 signal. It wasn't connected.

With TOS 1.0 the address $FC0464 is a

Code: Select all

jmp $FC0020
but I cannot root the source of this behaviour.
Image


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