Afaik there is no such documentation.
However, every build I have seen of these maintain two state machines in logic, one simulating a 8MHz CPU towards the bus, and one simulating a xxMHz bus towards the CPU. So yes, waitstates are inserted as needed. (at 16MHz it's pretty easy to do, it get's more complicated at higher speeds.)
If you want to look closer at an accelerator implementing this I suggest the Mach16 buid from http://atari4ever.free.fr/