So I got some 20ns SRAM to replace my cache and after that I was able to enable the cache at 16MHz.
So the cache can work with faster SRAM.
I ran into more issue mostly on the 8 to 16MHz switch. If the system clock (from the 68000 socket) is directly connected to the 68020, the 8 to 16 MHz switch works most of the time (I still get some craches 3 out 5 times on boot when CPX are loaded as GENERAL.CPX is what does the frequency switch).
Once at 16MHz I can enable the cache. If I save the config with 16MHz with cache enable, it's almost a 100% crash are CPX load time.
So I think that when the MSTE switch frequency the switch is not clean and we get some glitches that the 68020 doesn't like (but apparently doesn't cause issues with the 68000 .. probably because it's slower). I'm guessing a DTACK arrives to early, the 68020 decodes it (even though we delay by 1 clock cycle to resync with the ST on a 4 clock cycle) and tries to read data on the bus when it's not yet valid. We might not have that issue later when we run the 68020 at full 32MHz async.
Also, the MSTE doesn't support enabling the cache at 8MHz (I wanted to test 8/32 MHz with cache).
If you write $FD (8MHz with cache) to $ffff8e21.w and re-read it, it return $FC .. aka 8MHz no cache.
I've look at the MSTE cache schematics and will see if there is a way to force enable the cache by forcing one of the GAL signal (not sure that's going to work but I'll see).
The pure gain of just the 68020 is not that great overall. Also this is with our first version of the CPLD code. A lot of progress has been made but I didn't have time to test the new code on this machine yet. I'll try to post some result at 8/32 (without the cache for now) to show the difference the
clock can make.
Code: Select all
MegaSTE 68000 at 16MHz with 16K cache MegaSTE 68020 at 16MHz with 16K cache
GEM Bench v4.03 Ω Ofir Gal - 3 March 95 GEM Bench v4.03 Ω Ofir Gal - 3 March 95
Mega STE TOS 2.06 Mega STE TOS 2.06
AES v3.20 AES v3.20
GEMDOS v0.32 GEMDOS v0.32
MiNT not present MiNT not present
Blitter Enabled Blitter Enabled
NVDI not present NVDI not present
Video Mode: 640*400*2 Video Mode: 640*400*2
FPU not present FPU not present
Run and Malloc from STRAM Run and Malloc from STRAM
Ref: MSTE + Blitter, ST High Ref: MSTE + Blitter, ST High
GEM Dialog Box: 4.745 96% GEM Dialog Box: 5.220 87%
VDI Text: 5.040 99% VDI Text: 5.605 89%
VDI Text Effects: 12.250 100% VDI Text Effects: 11.400 107%
VDI Small Text: 5.520 99% VDI Small Text: 6.170 88%
VDI Graphics: 14.230 100% VDI Graphics: 11.055 128%
GEM Window: 1.340 98% GEM Window: 1.410 93%
Integer Division: 8.815 100% Integer Division: 3.095 286%
Float Math: 7.170 101% Float Math: 7.130 101%
RAM Access: 3.155 99% RAM Access: 2.005 157%
ROM Access: 3.145 100% ROM Access: 2.030 155%
Blitting: 1.740 100% Blitting: 1.785 97%
VDI Scroll: 3.925 101% VDI Scroll: 4.135 96%
Justified Text: 4.850 100% Justified Text: 5.310 91%
VDI Enquire: 1.755 94% VDI Enquire: 1.790 93%
New Dialogs: 6.065 95% New Dialogs: 6.325 91%
Graphics: 98% Graphics: 96%
CPU: 100% CPU: 174%
Average: 98% Average: 117%