68020 booster

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rpineau
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Re: 68020 booster

Postby rpineau » Mon Nov 30, 2015 11:26 pm

so we still have some instability but when using the 32MHz clock from the mother board on a STE and doing 8/32MHz switching here are some result with and without blitter. I suspect some of the Genbench loops aren't correct because of the instruction cache :

Blitter OFF :
GEM Bench v4.03 Ω Ofir Gal - 3 March 95
============================================
STE TOS 2.06
AES v3.20
GEMDOS v0.32
MiNT not present
Blitter Disabled
NVDI not present
Video Mode: 640*200*4
FPU not present
Run and Malloc from STRAM
Ref: STE, No Blitter, ST Medium
============================================
GEM Dialog Box: 7.925 99%
VDI Text: 12.035 116%
VDI Text Effects: 20.495 118%
VDI Small Text: 12.645 107%
VDI Graphics: 10.485 180%
GEM Window: 2.355 139%
Integer Division: 1.585 1135%
Float Math: 14.560 91%
RAM Access: 3.120 202%
ROM Access: 3.095 203%
Blitting: 3.970 222%
VDI Scroll: 8.420 160%
Justified Text: 10.450 131%
VDI Enquire: 3.190 83%
New Dialogs: 9.455 100%
============================================
Graphics: 132%
CPU: 407%
Average: 205%


Blitter ON :
GEM Bench v4.03 Ω Ofir Gal - 3 March 95
============================================
STE TOS 2.06
AES v3.20
GEMDOS v0.32
MiNT not present
Blitter Enabled
NVDI not present
Video Mode: 640*200*4
FPU not present
Run and Malloc from STRAM
Ref: STE + Blitter, ST Medium
============================================
GEM Dialog Box: 6.910 81%
VDI Text: 6.770 85%
VDI Text Effects: 11.620 103%
VDI Small Text: 7.735 85%
VDI Graphics: 10.400 165%
GEM Window: 1.860 85%
Integer Division: 1.585 1132%
Float Math: 14.560 91%
RAM Access: 3.115 202%
ROM Access: 3.095 203%
Blitting: 1.490 93%
VDI Scroll: 4.760 92%
Justified Text: 6.420 87%
VDI Enquire: 3.190 83%
New Dialogs: 8.850 87%
============================================
Graphics: 95%
CPU: 407%
Average: 178%


We think we might still have issue in the /BR, /BG, /BGACK code which causes issues with the blitter.
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Re: 68020 booster

Postby exxos » Mon Nov 30, 2015 11:35 pm

Nice :)

for comparison, this is 32mhz on STFM vs 16mhz also..
res2.jpg


GemBench is screwed with the cache unfortunately, but will be fixed one day ;)
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Re: 68020 booster

Postby rj1 » Wed Dec 02, 2015 3:52 pm

I hope Rodolphe doesn't mind me giving an update in his thread :)

We tried to run the STE bus in 3 clock cycles - that isn't very stable yet but it shows nice boost again:

Blitter ON:

Code: Select all

GEM Bench v4.03             ˝ Ofir Gal - 3 March 95
============================================
STE  TOS 2.06
AES v3.20
GEMDOS v0.32
MiNT not present
Blitter Enabled
NVDI not present
Video Mode: 640*200*4
FPU not present
Run and Malloc from STRAM
Ref: STE + Blitter, ST Medium
============================================
GEM Dialog Box:             5.440    103%
VDI Text:                   5.560    103%
VDI Text Effects:           9.565    126%
VDI Small Text:             6.315    104%
VDI Graphics:               8.275    207%
GEM Window:                 1.505    105%
Integer Division:           1.570   1143%
Float Math:                12.090    110%
RAM Access:                 3.020    208%
ROM Access:                 2.575    244%
Blitting:                   1.320    105%
VDI Scroll:                 4.105    107%
Justified Text:             5.290    105%
VDI Enquire:                2.475    107%
New Dialogs:                7.005    110%
============================================
Graphics:                            116%
CPU:                                 426%
Average:                             199%


Blitter OFF:

Code: Select all

GEM Bench v4.03             ˝ Ofir Gal - 3 March 95
============================================
STE  TOS 2.06
AES v3.20
GEMDOS v0.32
MiNT not present
Blitter Disabled
NVDI not present
Video Mode: 640*200*4
FPU not present
Run and Malloc from STRAM
Ref: STE, No Blitter, ST Medium
============================================
GEM Dialog Box:             6.285    125%
VDI Text:                  10.145    138%
VDI Text Effects:          17.430    138%
VDI Small Text:            10.560    129%
VDI Graphics:               8.395    225%
GEM Window:                 1.955    167%
Integer Division:           1.570   1146%
Float Math:                12.095    110%
RAM Access:                 3.020    208%
ROM Access:                 2.580    244%
Blitting:                   3.130    281%
VDI Scroll:                 6.915    195%
Justified Text:             8.860    155%
VDI Enquire:                2.470    107%
New Dialogs:                7.460    127%
============================================
Graphics:                            162%
CPU:                                 427%
Average:                             233%


For regular 4 clock cycle access, we fixed some equations and the below 100% results Rodolphe shown are now fixed.

J

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Re: 68020 booster

Postby rpineau » Wed Dec 02, 2015 6:48 pm

Off course you can post update :) (if you do that means I don't have to do it :) ).
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Re: 68020 booster

Postby rpineau » Sun Dec 06, 2015 7:31 pm

I manage to run more test (as did Juliusz) and we now have better result with the 8/32 MHz switching :

Code: Select all

GEM Bench v4.03             Ω Ofir Gal - 3 March 95
============================================
Mega STE  TOS 2.06
AES v3.20
GEMDOS v0.32
MiNT not present
Blitter Enabled
NVDI not present
Video Mode: 640*400*2
FPU not present
Run and Malloc from STRAM
Ref: STE + Blitter, ST High
============================================
GEM Dialog Box:             5.485    100%
VDI Text:                   5.315    103%
VDI Text Effects:          10.665    138%
VDI Small Text:             5.840    104%
VDI Graphics:              11.255    209%
GEM Window:                 1.530    103%
Integer Division:           1.560   1153%
Float Math:                10.735    124%
RAM Access:                 2.945    213%
ROM Access:                 2.535    248%
Blitting:                   1.720    106%
VDI Scroll:                 3.970    107%
Justified Text:             5.105    106%
VDI Enquire:                2.480    107%
New Dialogs:                7.010    108%
============================================
Graphics:                            117%
CPU:                                 434%
Average:                             201%



Not a huge improvement but faster is always good.

We have a few issues on MegaSTE :
    * If we enable the 16KB cache : freeze
    * When in 8/32 mode when general.cpx switch to 16MHz no cache: freeze.
So the switch from 8 to 16MHz on the mother board probably create a glitch. If I set the jumper to directly get sys_clk from the mother board (so no 32MHz switching), the machine works fine and switch ok from 8 to 16MHZ (mother board).

As the goal is to run always at 32MHz for the CPU we're not going to spend to much time tracking the issue with 8/32 to 16/32 switching.
As for the MSTE cache, I'm still trying to figure out what's going on but I haven't had time to put the logic analyzer on it (may be next weekend).

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Re: 68020 booster

Postby rpineau » Sun Dec 13, 2015 6:20 pm

More progress are being made. I also started looking at the MegaSTE cache issue. The SRAM are 70ns so there might be some issue there where DTACK (which become DSACK1) is issued on a 68020 state when the CPU is already in wait state and finishes the cycle immediately, grabbing data on the bus before the SRAM has put it on it. If the data is not correct this would definitely crash the 68020. With the logic analyzer I can definitely see a few cache access (cache /CS is set to LO as soon as you activate the cache and then MATCH from the tag RAM pulses when there is a match on the address). It crashes very quickly. I've ordered some 20ns replacement SRAM for the cache (the TAG RAM is 25 ns so that's fine) to see if this can help. If not I'll have to delay DTACK when the cache is active and we have a MATCH, which mean I need 2 pins on the board.. and I only have one ..
When Juliusz got his card there was issues on 2 pins so he rewired them to 2 of the extra pin we had on the board. I did some test with mine and didn't see that issue so I might temporary revet the mod to get back 2 pins and test delaying DTACK when the cache is accessed.

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Re: 68020 booster

Postby shoggoth » Mon Dec 14, 2015 8:20 am

A 020-equipped MSTE + cache support would be a really really nice machine.

Keep up the good work!
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Re: 68020 booster

Postby rpineau » Fri Dec 25, 2015 2:05 am

So I got some 20ns SRAM to replace my cache and after that I was able to enable the cache at 16MHz.
So the cache can work with faster SRAM.
I ran into more issue mostly on the 8 to 16MHz switch. If the system clock (from the 68000 socket) is directly connected to the 68020, the 8 to 16 MHz switch works most of the time (I still get some craches 3 out 5 times on boot when CPX are loaded as GENERAL.CPX is what does the frequency switch).
Once at 16MHz I can enable the cache. If I save the config with 16MHz with cache enable, it's almost a 100% crash are CPX load time.
So I think that when the MSTE switch frequency the switch is not clean and we get some glitches that the 68020 doesn't like (but apparently doesn't cause issues with the 68000 .. probably because it's slower). I'm guessing a DTACK arrives to early, the 68020 decodes it (even though we delay by 1 clock cycle to resync with the ST on a 4 clock cycle) and tries to read data on the bus when it's not yet valid. We might not have that issue later when we run the 68020 at full 32MHz async.
Also, the MSTE doesn't support enabling the cache at 8MHz (I wanted to test 8/32 MHz with cache).
If you write $FD (8MHz with cache) to $ffff8e21.w and re-read it, it return $FC .. aka 8MHz no cache.
I've look at the MSTE cache schematics and will see if there is a way to force enable the cache by forcing one of the GAL signal (not sure that's going to work but I'll see).
The pure gain of just the 68020 is not that great overall. Also this is with our first version of the CPLD code. A lot of progress has been made but I didn't have time to test the new code on this machine yet. I'll try to post some result at 8/32 (without the cache for now) to show the difference the
clock can make.

Code: Select all

MegaSTE 68000 at 16MHz with 16K cache                   MegaSTE 68020 at 16MHz with 16K cache

GEM Bench v4.03             Ω Ofir Gal - 3 March 95     GEM Bench v4.03             Ω Ofir Gal - 3 March 95
============================================            ============================================
Mega STE  TOS 2.06                                      Mega STE  TOS 2.06
AES v3.20                                               AES v3.20
GEMDOS v0.32                                            GEMDOS v0.32
MiNT not present                                        MiNT not present
Blitter Enabled                                         Blitter Enabled
NVDI not present                                        NVDI not present
Video Mode: 640*400*2                                   Video Mode: 640*400*2
FPU not present                                         FPU not present
Run and Malloc from STRAM                               Run and Malloc from STRAM
Ref: MSTE + Blitter, ST High                            Ref: MSTE + Blitter, ST High
============================================            ============================================
GEM Dialog Box:             4.745     96%               GEM Dialog Box:             5.220     87%
VDI Text:                   5.040     99%               VDI Text:                   5.605     89%
VDI Text Effects:          12.250    100%               VDI Text Effects:          11.400    107%
VDI Small Text:             5.520     99%               VDI Small Text:             6.170     88%
VDI Graphics:              14.230    100%               VDI Graphics:              11.055    128%
GEM Window:                 1.340     98%               GEM Window:                 1.410     93%
Integer Division:           8.815    100%               Integer Division:           3.095    286%
Float Math:                 7.170    101%               Float Math:                 7.130    101%
RAM Access:                 3.155     99%               RAM Access:                 2.005    157%
ROM Access:                 3.145    100%               ROM Access:                 2.030    155%
Blitting:                   1.740    100%               Blitting:                   1.785     97%
VDI Scroll:                 3.925    101%               VDI Scroll:                 4.135     96%
Justified Text:             4.850    100%               Justified Text:             5.310     91%
VDI Enquire:                1.755     94%               VDI Enquire:                1.790     93%
New Dialogs:                6.065     95%               New Dialogs:                6.325     91%
============================================            ============================================
Graphics:                             98%               Graphics:                             96%
CPU:                                 100%               CPU:                                 174%
Average:                              98%               Average:                             117%
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Re: 68020 booster

Postby rpineau » Tue Dec 29, 2015 8:11 pm

Quick update, MegaSTE 8/32 MHz without the 16KB cache :

Code: Select all

GEM Bench v4.03             Ω Ofir Gal - 3 March 95
============================================
Mega STE  TOS 2.06
AES v3.20
GEMDOS v0.32
MiNT not present
Blitter Enabled
NVDI not present
Video Mode: 640*400*2
FPU not present
Run and Malloc from STRAM
Ref: MSTE + Blitter, ST High
============================================
GEM Dialog Box:             4.840     94%
VDI Text:                   4.510    111%
VDI Text Effects:           9.145    134%
VDI Small Text:             4.875    112%
VDI Graphics:              10.275    138%
GEM Window:                 1.380     95%
Integer Division:           1.560    567%
Float Math:                10.705     67%
RAM Access:                 2.940    107%
ROM Access:                 2.075    151%
Blitting:                   1.650    105%
VDI Scroll:                 3.575    111%
Justified Text:             4.450    109%
VDI Enquire:                2.295     72%
New Dialogs:                6.340     91%
============================================
Graphics:                            106%
CPU:                                 223%
Average:                             137%
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Re: 68020 booster

Postby frank.lukas » Tue Dec 29, 2015 8:51 pm

Integer Division: 1.560 567%

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Re: 68020 booster

Postby rpineau » Tue Dec 29, 2015 9:32 pm

Yep, and that's compared to a Mega STE at 16MHz with cache. I we compare the same result to a STE (so 68000 at 8MHz, no cache), the integer division speedup is 1153 % (as seen a few post above).
So I think we have a stable 8/32 mode for STE and MegaSTE. Time to start the work on running the CPU at 32MHz all the time.
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Re: 68020 booster

Postby GadgetUK164 » Sun Jan 03, 2016 1:28 pm

Great work on this so far! Very impressed! Are you going to add any ALTRAM or something onto these - that's where the real boost will come in (assuming theres software to use it).

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Re: 68020 booster

Postby rpineau » Sun Jan 03, 2016 7:26 pm

There's going to be a card with AtlRAM on the expansion port.
The main board will have the CPU, CPLD and 32bit TOS (2x 44 pin PLCC ROM). Everything else after that will be on the expansion port (AltRAM using SRAM, .... ).
The expansion connector has all the signals of the 68020 (and will be fully documented :) .. no point in having an expansion port is nobody can use it :) ).
The prototype uses a 3x32 pin connector (similar for factor as the VME connector), but the final version will use a 2x48 header (similar to the CT60, but for the 68020). If people have better idea for the expansion slot form factor, let us know.
Rodolphe
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Re: 68020 booster

Postby rpineau » Thu Jan 28, 2016 7:17 pm

Quick update.
We've made some progress on running at constant 32MHz.. but it crashes on memory test and other bus access. So not there yet.
We're also running into issues with the CPLD IDE (WinCUPL) that make coding on this very ... painful to be polite. So we've made the decision to do a v2 board and use a Xilinx CPLD : XC95144XL (100-pin TQFP). This means a new round of board, learning to solder these with my new reflow oven (aka learning to lay down the solder paste in the right quantity then fix bridges between pin), learning the Xilinx tools (and VHDL)...
So we're making progress and learning from our mistakes along the way.
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Re: 68020 booster

Postby pakman » Fri Jan 29, 2016 9:53 pm

rpineau wrote:So we've made the decision to do a v2 board and use a Xilinx CPLD : XC95144XL (100-pin TQFP). This means a new round of board, learning to solder these with my new reflow oven (aka learning to lay down the solder paste in the right quantity then fix bridges between pin), learning the Xilinx tools (and VHDL)...

Good decision.
Save one prototype board for me.

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Re: 68020 booster

Postby rpineau » Sat Jan 30, 2016 4:39 am

As soon as I have prototype I'll let you know.
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Re: 68020 booster

Postby Soap » Sat Jan 30, 2016 7:30 pm

Following this closely as I too have a Mega STe 4 and would be interested depending on price.

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Re: 68020 booster

Postby rj1 » Sun May 22, 2016 1:04 pm

Update: no, this project is not dead :)
After switching to Xilinx, new board is now ready and we continue with development.
We already have part of the VHDL code written.

020.jpg
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Re: 68020 booster

Postby jvas » Sun May 22, 2016 4:42 pm

Looks really professional!

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Re: 68020 booster

Postby Arne » Sat May 28, 2016 8:49 am

Have you already decided on type and pinout of your expansion connector?
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Re: 68020 booster

Postby rpineau » Sat May 28, 2016 4:18 pm

Sort of.
As you can see on the picture above it uses standard pins on a normal pitch with all the 68020 signals.
I can publish the pinout but this might evolve.
IT has 2 connectors, one 56 pins at the top and one 40 pin t the bottom.
But I'm open to suggestion if you have better ideas. The advantage of this expansion is that it's cheap.
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Re: 68020 booster

Postby Arne » Sat May 28, 2016 6:59 pm

Didn't you use a DIN 41612 (same as TT-FastRAM) on your first prototype?
If you exchange /STERM, /CBACK and /CBREQ for /DSACK0 and /DSACK1 it should be fine. Or not?
But it's your choice. I'd be fine with 40/56 connector, too. :D
As long as you tell us the pinout.
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Re: 68020 booster

Postby rpineau » Sat May 28, 2016 7:30 pm

Yes I did use a DIN 41612 on the proto. But these connector aren't cheap so we decided to go with simple pins.
As for the pinout, here is the temporary one :

Code: Select all

BGI_CPU and BGO_CPU work the same way as on the Falcon.
CPU BG -> BGI_CPU [EXP cards] BGO_CPU -> XC95144XL -> ST BG (if needed)

56 pins top connector
 1 - /DS
 2 - /AS
 3 - R/W
 4 - /HALT
 5 - /BERR
 6 - /DSACK0
 7 - /DSACK1
 8 - GND
 9 - /BGACK
10 - /BR
11 - /BGI_CPU
12 - /BGO_CPU
13 - /RESET
14 - CLK (32MHZ)
15 - /RMC
16 - FC0
17 - FC1
18 - FC2
19 - /SIZ0
20 - /DBEN
21 - /SIZ1
22 - /ECS
23 - /IPEND
24 - /OCS
25 - A31
26 - A30
27 - A29
28 - A28
29 - A27
30 - A26
31 - A25
32 - A24
33 - A23
34 - A22
35 - A21
36 - A20
37 - A19
38 - A18
39 - A17
40 - A16
41 - A15
42 - A14
43 - A13
44 - A12
45 - A11
46 - A10
47 - A9
48 - A8
49 - A7
50 - A6
51 - A5
52 - A4
53 - A3
54 - A2
55 - A1
56 - A0

40 pins bottom connector
57 - /AVEC
58 - /IPL0
59 - /IPL1
60 - /IPL2
61 - VCC (5V)
62 - VCC (5V)
63 - GND
64 - GND
65 - D31
66 - D30
67 - D29
68 - D28
69 - D27
70 - D26
71 - D25
72 - D24
73 - D23
74 - D22
75 - D21
76 - D20
77 - D19
78 - D18
79 - D17
80 - D16
81 - D15
82 - D14
83 - D13
84 - D12
85 - D11
86 - D10
87 - D9
88 - D8
89 - D7
90 - D6
91 - D5
92 - D4
93 - D3
94 - D2
95 - D1
96 - D0


I'll put it in a Eagle library by itself and post it here soon (it's in one of my other library for now).
Last edited by rpineau on Sun Jun 05, 2016 6:36 pm, edited 1 time in total.
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Re: 68020 booster

Postby rpineau » Sat May 28, 2016 7:38 pm

and the Eagle library.
68020_exp.zip
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Last edited by rpineau on Sun Jun 05, 2016 6:34 pm, edited 1 time in total.
Falcon + AB040 + Eclipse PCI + ATI Rage VGA card + NE2000 Ethernec + HxC Floppy Emulator
MegaSTE 4MB + CosmosEx / 1040 STF for hardware dev
http://www.rti-zone.org/atari.php

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Re: 68020 booster

Postby Arne » Sun May 29, 2016 6:30 am

Thanx but I will wait till you decided for the final pinout/layout.
You used an oscillator for the CPU clock? If so: why no PLL? It would give you synchronism.
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