Now for the next question(s)
As we plan on having add-on cards, these card could potentially need to trigger some interrupt.
On the STF, Mega ST and STE, IPL5 is available. But on the MSTE it's used by the SCC (Z85C30).
So my idea is to use the VHDL code from Suska for the MFP 68901 to manage interrupt on level 5 (more on this latter for the MSTE).
I already trim down the code to only have the GPIO pin as interrupt source (no more timer or serial port in there, no output on the GPIO). This gives us 8 interrupt pin that will be wired as IRQ0 to IRQ7 on the expansion port. It as not easy to make this fit in a XC95144XL but for now it does.. even though this hasn't been tested yet so I might have broke it
Anyway.. As this is based on the MFP I plan on having it at the same address as the TT MFP and use the same interrupt vector range from $140 to $17c.
I might fix the vector register (which would save more space) and fix the bit of the interrupt vector register to 1 (software terminated interrupt) as this is what the TOS sets by default on the ST and TT for the MFP so people are already used to this.
So this would allow 8 level on interrupt mapped to level 5.
As on the MSTE it's used by the SCC we will have to daisy chain this interrupt controller and the SCC using the /IEI pin (the SCC allows this as well as the MFP)... which mean 1 wire has to be soldered on a pin of the SCC ... which is in a PLCC socket (at least on my MSTE). So it will be a wire to the /IEO pin of the SCC (pin 7) which is currently not connected to anything (so we can't find it anywhere but on the SCC socket or the SCC itself).
The other option is to not have an interrupt controller and let cards deal with interrupt vectors and checking if there is an interrupt in progress before triggering a new one (still has to be level 5). The goal here is to make it easier to build add-on card by putting as much of the logic as possible on the CPU card.
So.. what do you guys think ?